MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 747

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

26.2.1.11 FIFOC Interrupt Register (FIFOC_INT)
26.2.1.12 FIFOC DMA Request Register (FIFOC_DMA)
Freescale Semiconductor
FIFOC RX DMA REQUEST FIFOC RX DMA REQUEST. There is one bit per PSC FIFO showing all PSCs with currently
FIFOC TX DMA REQUEST FIFOC TX DMA REQUEST. There is one bit per PSC FIFO showing all PSCs with currently
Address: FIFOC Base + 0x04
Address: FIFOC Base + 0x08
FIFOC RX INTERRUPT FIFOC RX Interrupt. There is one bit per PSC FIFO showing all PSCs with currently pending
FIFOC TX INTERRUPT FIFOC TX Interrupt. There is one bit per PSC FIFO showing all PSCs with currently pending
Reset
Reset
Reset
Reset
R
R
W
W
W
W
R
R
Field
Field
16
16
0
0
0
0
0
0
17
17
0
0
0
0
1
1
18
18
interrupts.
interrupts.
0
0
0
0
2
2
Figure 26-13. FIFOC DMA Request Register (FIFOC_DMA)
pending requests.
pending requests.
Figure 26-12. FIFOC Interrupt Register (FIFOC_INT)
19
19
0
0
0
0
3
3
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 26-15. FIFOC_DMA field descriptions
Table 26-14. FIFOC_INT field descriptions
20
20
4
0
0
4
0
0
21
21
0
0
0
0
5
5
22
22
0
0
0
0
6
6
23
23
0
0
0
0
7
7
FIFOC RX DMA REQUEST[PSC9:PSC0]
FIFOC TX DMA REQUEST[PSC9:PSC0]
Description
24
24
8
FIFOC RX INTERRUPT[PSC9:PSC0]
0
0
8
0
0
FIFOC TX INTERRUPT[PSC9:PSC0]
Description
25
25
9
0
0
9
0
0
10
26
10
26
0
0
0
0
PSC Centralized FIFO Controller (FIFOC)
11
27
11
27
0
0
0
0
12
28
12
28
0
0
0
0
Access: User read-only
Access: User read-only
13
29
13
29
0
0
0
0
14
30
14
30
0
0
0
0
26-13
15
31
15
31
0
0
0
0