MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 103

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Many peripheral clocks may be disabled to reduce power consumption. See
Clock Control Register 1 (SCCR1),”
5.2.2
The system oscillator can be disabled to allow an externally generated clock to be used as a reference. This
can be performed by setting the RST_CONF_SYSOSCEN in the reset configuration word (RST_CONF)
at reset.
5.2.3
Each PSC can select from multiple clock sources. A single clock input is provided that allows the
PSC_MCLK_IN to be used as a master reference by all PSCs. Additionally, clock gating is supplied
allowing the shutdown of unnecessary clocks.
This circuit is replicated for each PSC and can be controlled by accessing the PSC Clock Control Registers
(see
1. PSC_MCLK_IN and CAN_CLK_IN are generated by external pins.
Freescale Semiconductor
Section 5.3.1.8, “PSC0 Clock Control Register (P0CCR),”
System Oscillator Disable
PSC Clock Generation
PSC_MCLK_IN
CAN_CLK_IN
1
2
SYS_CLK
REF_CLK
For all clock sources, see
For all clock sources, see
SDHC1, SDHC2
USB1, USB2
Peripheral
SYS_PLL
PSC[0:9]
Table 5-2. Peripheral Clock Reference (continued)
WDT
MCLK_0_SRC
RTC
TLM
MPC5125 Microcontroller Reference Manual, Rev. 2
Figure 5-2. PSC (MCLK) Clock Generation
for more information.
MCLK_EN
Clock
Gate
ips_clk
ips_clk, rtc_clk
ips_clk, sdhc_clk
ref_clk
tck
ips_clk, usb_clk
ips_clk, ref_clk
Section 5.2.4, “MSCAN Clock Generation.”
Section 5.2.3, “PSC Clock Generation.”
mclk_div
2
MCLK_DIV
Reserved
Reference Clock
MCLK_1_SRC
and subsequent sections).
1
PSC_MCLK_OUT
Section 5.3.1.2, “System
Clocks and Low-Power Modes
5-3