MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 827

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Chapter 31
Temperature Sensor
31.1
Introduction
The temperature sensor module monitors the internal temperature of the MPC5125. The temperature
sensor module asserts two internal signals. The first signal is TEMP_105. The TEMP_105 signal asserts
at one of eight programmable levels: 35 ºC, 45 ºC, 55 ºC, 65 ºC, 75 ºC, 85 ºC, 95 ºC, or 105 ºC. When the
TEMP_105 signal asserts, an interrupt is signaled (if enabled) to the CPU core. The second signal,
TEMP_125, is set to assert when the chip temperature reaches or exceeds 125 °C. When the TEMP_125
signal asserts, a machine check exception is signaled to the CPU core. In either case, some type of machine
check exception handler or interrupt service routine must be called that starts reducing the power
consumption of the device, possibly by shutting down various modules or setting clocks to lower
frequencies, etc.
The temperature measurement accuracy is limited to ±5 °C.
31.1.1
Normal Operation Mode
From the release of HRESET, the temperature sensor module is enabled and running. The TEMP_105 and
TEMP_125 signals are active. There are several registers that control the state and condition of the
temperature sensor module. These registers are located in modules other than the temperature sensor
module and are described in detail there.
The temperature sensor module can be enabled or powered down by use of the TEMPPD Bit in the
Section 2.3.1.1.2, “System Priority Configuration Register (SPCR).”
Setting the TEMPPD bit to a logic 0
enables the temperature sensor module. Setting TEMPPD bit to a logic 1 puts the temperature sensor
module in a power down condition. Powering down the temperature sensor module prevents it from
asserting either the TEMP_105 or TEMP_125 signals.
The TEMP_105 can be programmed to one of eight temperature trip levels. The trip temperature is
programmed using the TEMPSEL bits in the c.
The TEMP_125 signal is programmed to assert when the chip temperature reaches or exceeds 125 °C. This
temperature cannot be changed. When the TEMP_125 signal asserts, the TEMP125C bit sets in the
Section 20.3.1.15, “System Error Status Register (SERSR).”
If unmasked, the TEMP125C bit creates a
machine check exception. The TEMP125C bit can be masked by the TEMP125C bit in the
Section 20.3.1.16, “System Error Mask Register (SERMR).”
The default state of the TEMP125C bit in the
Section 20.3.1.16, “System Error Mask Register (SERMR),”
is a logic 0 meaning that the TEMP_125C
signal does not create a machine check exception. Setting the TEMP125C bit in the SERMR to a logic 1
allows the TEMP_125 signal to create a machine check exception.
MPC5125 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor
31-1