MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 386

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Fast Ethernet Controller (FEC)
14.3.5.22 FIFO Receive Start (ETH_R_FSTART) Register
The FIFO Receive Start (ETH_R_FSTART) register is programmed to indicate the starting address of the
receive FIFO. The transmit FIFO uses addresses from 0 to R_FSTART – 4. The receive FIFO uses
addresses from R_FSTART to ETH_R_BOUND[R_BOUND] – 1, inclusive.
The ETH_R_FSTART register is initialized by hardware at reset. Write ETH_R_FSTART to change the
default value.
14.3.5.23 Beginning of Receive Descriptor Ring (ETH_R_DES_START) Register
The Beginning of Receive Descriptor Ring (ETH_R_DES_START) register is a pointer to the start of the
circular receive buffer descriptor queue in external memory. This pointer must be 32-bit aligned; Write bits
30, 31 to 0. It is strongly recommended to be quad word-aligned (evenly divisible by 16) to get better
system performance; write bits 28, 29, 30, and 31 to 0.
This register is not reset and must be initialized prior to operation.
14-30
Address: Base + 0x150
R_FSTART
R_BOUND
Reset
Reset
Field
Field
W
W
R
R
16
0
0
0
0
0
Read-only. Determines the highest valid FIFO RAM address.
This is the address of the first receive FIFO location. It acts as a delimiter between the receive and transmit
FIFOs.
17
0
0
0
0
1
18
0
0
0
0
2
Figure 14-23. FIFO Receive Start (ETH_R_FSTART) Register
19
0
0
0
0
3
Table 14-27. ETH_R_FSTART field descriptions
Table 14-26. ETH_R_BOUND field descriptions
MPC5125 Microcontroller Reference Manual, Rev. 2
20
4
0
0
0
0
21
0
0
1
1
5
22
0
0
0
6
23
0
0
1
7
Description
Description
24
8
0
0
0
R_FSTART
25
9
0
0
0
10
26
0
0
0
11
27
0
0
0
12
28
0
0
0
Freescale Semiconductor
Access: User read/write
13
29
0
0
0
14
30
0
0
0
0
15
31
0
0
0
0