MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 101

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Chapter 5
Clocks and Low-Power Modes
5.1
The wide range of applications supported by the MPC5125 requires a complex clocking structure with
different primary clock domains derived from an oscillator source. Internal PLL and clock dividers allow
generation of a wide range of clock references.
Each peripheral clock may be individually controlled to minimize total power consumption of the device.
Clocks may be gated individually or scaled in frequency to ensure the most efficient power profile for the
user’s application.
5.2
The system reference is provided by a crystal oscillator that drives the system PLL. This PLL is
programmed at reset by the reset configuration word (RST_CONF) sampled at the rising edge
(deassertion) of power on reset (PORESET). See
SYS_PLL clock is then divided (SYS_DIV) and used as a reference to the MPC5125 cores and
peripherals.
Freescale Semiconductor
XTALO
RST_CONF_SYSOSCEN
XTALI
Introduction
System Clock Generation
SYS_
OSC
REF_CLK
SPMF[3:0]
SYS
PLL
MPC5125 Microcontroller Reference Manual, Rev. 2
SPLL_OUT
Figure 5-1. MPC5125 Clock System
SYSDIV[5:0]
SYS_DIV
Section 4.2, “(PORESET) Power-On Initialization.”
SYS_CLK
1/2
Power Arch.
CPMF[3:0]
IPS_DIV
PLL
ddr_clk
SDHC_DIV
LPC_DIV
NFC_DIV
DIU_DIV
1/2
sdhc1_clk
nfc_flash_clk
sdhc2_clk
diu_clk
DDR
Memory
Device
csb_clk
ppc_clk
ips_clk
lpc_clk
The
5-1