MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 957

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

When the endpoint is an isochronous OUT, there are only start-splits and no complete-splits. When the
endpoint is an isochronous IN, there is at most one start-split and one to N complete-splits. The scheduling
boundary cases are:
Freescale Semiconductor
•
•
Periodic Schedule
Start & Complete
End of H-Frame
HS/FS/LS Bus
Case 1: The entire split transaction is completely bounded by an H-Frame. For example, the
start-splits and complete-splits are all scheduled to occur in the same H-Frame.
Case 2a: This boundary case is where one or more (at most two) complete-splits of a split
transaction IN are scheduled across an H-Frame boundary. This can only occur when the split
transaction has the possibility of moving data in B-Frame, micro-frames 6 or 7 (H-Frame
micro-frame 7 or 0). When an H-Frame boundary wrap condition occurs, the scheduling of the split
transaction spans more than one location in the periodic list (for example, it takes two siTDs in
adjacent periodic frame list locations to fully describe the scheduling for the split transaction).
Frame Wrap at
Micro-Frame 0
Micro-Frame
Micro-Frame
Normal Case
in H-Frame,
Figure 32-68. Split Transaction and Isochronous Scheduling Boundary Conditions
Case 2a:
Case 2b:
Case 1:
B-Frame N–1
7
6
0
7
MPC5125 Microcontroller Reference Manual, Rev. 2
S
C
S
S
0
6
1
0
S
1
2
1
C
S
C
2
0
0
3
2
H-Frame N
C
S
C
3
1
1
siTD
4
3
B-Frame N
x
OUT
IN
C
S
C
S
2
0
2
5
4
C
C
S
1
3
3
6
5
Universal Serial Bus Interface with On-The-Go
C
S
C
2
0
4
7
6
C
C
S
1
3
5
IN
0
7
OUT
S
IN
C
C
2
6
H-Frame N+1
siTD
1
0
C
3
B-Frame N+1
x+1
32-129