MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 333

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Chapter 12
Multi-port DRAM Controller Priority Manager
12.1
The multi-port DRAM controller services the highest priority request from five different buses using a
4-bit priority signal. This 4-bit priority is dynamically set by the DRAM controller priority manager based
on register settings and the most recent activity on each bus. In general, the DRAM priority manager
increases the priority of a channel if it has not been recently serviced and decreases the priority of channels
that have been recently serviced.
A block diagram of the priority manager is given in
for all five DRAM buses, and produces the priority signals for the five buses.
The priority manager uses an ACK-based schema; the priority depends on how many times for the last N
requests accepted by the DRAM controller the current owner of the bus won the request. A running
average counter keeps track of how many acknowledgements out of the last N acknowledgements have
been for a specific bus. This number is then put in a look-up table configurable by writing some config
registers. The output of the look-up table is the priority for the next request on this bus.
This priority schema is versatile because programming the look-up table allows controlling relative
priority to other channels and the average share of the bandwidth the current master gets. The priority
schema introduces fairness because the look-up table can be programmed to reduce the priority of a bus
that has won a large share of requests and increase the priority of a bus that lost a large share of requests.
Freescale Semiconductor
Introduction
IPMX0_PRIO(DIU)
IP Bus
IPMX0_REQ
IPMX1_REQ
IPMX2_REQ
IPMX3_REQ
IPMX4_REQ
IPMX0_ACK
IPMX1_ACK
IPMX2_ACK
IPMX3_ACK
IPMX4_ACK
MPC5125 Microcontroller Reference Manual, Rev. 2
Figure 12-1. Priority Manager Block Diagram
Priority Manager
IPS Interface
Figure
12-1. It accepts the request and ACK-signals
IPMX0_PRIO[3:0]
IPMX1_PRIO[3:0]
IPMX2_PRIO[3:0]
IPMX3_PRIO[3:0]
IPMX4_PRIO[3:0]
12-1