MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 409

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Freescale Semiconductor
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— The Ethernet controller manages as many as 7 dribbling bits when the receive frame terminates
CRC Error
— When a CRC error occurs with no dribble bits, the FEC closes the buffer and sets the CR bit in
Frame Length Violation
— When the receive frame length exceeds MAX_FL bytes, the BABT interrupt is generated and
Truncation
— When the receive frame length exceeds 2047 bytes, the frame is truncated and the TR bit is set
non-octet aligned and it checks the CRC of the frame on the last octet boundary. If there is a
CRC error, the frame non-octet aligned (no) error is reported in the receive BD. If there is no
CRC error, no error is reported.
the RxBD. CRC checking cannot be disabled, but the CRC error can be ignored if checking is
not required.
the LG bit in the end-of-frame receive BD is set. The frame is not truncated (truncation occurs
if the frame length exceeds 2047 bytes).
in the receive BD.
MPC5125 Microcontroller Reference Manual, Rev. 2
Fast Ethernet Controller (FEC)
14-53