MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 742

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PSC Centralized FIFO Controller (FIFOC)
26.2.1.4
Writing one to the interrupt bit clears the interrupt bit.
26-8
Address: Base + 0x8C (PSCn_TX_ISR)
MEM ERROR
DATA READY
Reset
Reset
ALARM
EMPTY
ORERR
FULL
Field
Field
W
W
R
R
Base + 0xCC (PSCn_RX_ISR)
16
0
0
0
0
0
Interrupt Status Register (ISR)
FIFO Alarm
0 The number of data in the FIFO has not reached the alarm level.
1 The number of data in the FIFO has reached the alarm level.
FIFO Full
0 The FIFO is not full.
1 The FIFO is full.
FIFO Empty
0 The FIFO contains data.
1 The FIFO is empty.
Memory Access Error. This bit is identical to the MEM error bit in the SR register. If the corresponding bit in
the IMR register also set, an interrupt is generated. Writing 1 to this bit clears the interrupt.
Data Ready. This is identical to the DATA READY bit in the SR register. If the corresponding bit in the IMR
register is also set, an interrupt is generated. Writing 1 to this bit clears the interrupt.
Overrun Error. This bit is identical to the ORERR bit in the SR register. If the corresponding bit in the IMR
register also set, an interrupt is generated. Writing 1 to this bit clears the interrupt.
17
0
0
0
0
1
18
0
0
0
0
2
19
0
0
0
0
3
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 26-6. SR field descriptions (continued)
Figure 26-5. Interrupt Status Register (ISR)
20
4
0
0
0
0
Table 26-7. ISR field descriptions
21
0
0
0
0
5
22
0
0
0
0
6
23
0
0
0
0
7
Description
Description
24
8
0
0
0
0
ERROR
MEM
w1c
25
9
0
0
0
READY
DATA
w1c
10
26
0
0
0
ERR
w1c
OR
11
27
0
0
0
ERR
w1c
UR
12
28
0
0
0
Freescale Semiconductor
Access: User read/write
ALARM FULL EMPTY
w1c
13
29
0
0
0
w1c
14
30
0
0
0
w1c
15
31
0
0
0