MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 929

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

32.6.8.1.1
This is the initial state. The state machine enters this state from Wait for Start Event when a start event as
defined in
state is to wait for the first observation of the head of the Asynchronous Schedule. This occurs when the
host controller fetches a queue head whose H-bit is set to a one.
32.6.8.1.2
This state is entered from the Wait for List Head state when the host controller fetches a queue head with
the H-bit set to a one. While in this state, the host controller performs nak counter reloads for every queue
head visited that has a non-zero nak reload value (RL) field.
32.6.8.1.3
This state is entered from the Do Reload state when a queue head with the H-bit set to a one is fetched.
While in this state, the host controller does not perform nak counter reloads.
32.6.9
This section presents an overview of how the host controller interacts with queuing data structures.
Queue heads use the queue element transfer descriptor (qTD) structure defined in
Element Transfer Descriptor (qTD).”
One queue head is used to manage the data stream for one endpoint. The queue head structure contains
static endpoint characteristics and capabilities. It also contains a working area from where individual bus
transactions for an endpoint are executed. Each qTD represents one or more bus transactions defined in
the context of the EHCI specification as a transfer.
Freescale Semiconductor
Section 32.6.7.5, “Asynchronous Schedule Traversal: Start Event,”
Managing Control/Bulk/Interrupt Transfers via Queue Heads
Figure 32-60. Example HC State Machine for Controlling Nak Counter Reloads
Wait for List Head
Do Reload
Wait for Start Event
QH.H == 1
Wait for List
MPC5125 Microcontroller Reference Manual, Rev. 2
Head
Start Event
Do Reload
Start Event
Wait for
Universal Serial Bus Interface with On-The-Go
QH.H == 1
occurs. The purpose of this
Section 32.5.5, “Queue
32-101