MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 137

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Chapter 6
Byte Data Link Controller (BDLC)
6.1
Introduction
The Byte Data Link Controller (BDLC) is a serial communication module that allows the user to send and
receive messages across a Society of Automotive Engineers (SAE) J1850 serial communication
network.
The user’s software manages each transmitted or received message on a byte-by-byte basis, while the
BDLC performs all of the network access, arbitration, message framing and error detection duties.
It is recommended that the reader be familiar with the operation and requirements of the SAE J1850
protocol as described in SAE Standard J1850 Class B Data Communications Network Interface document
prior to proceeding with this specification.
The BDLC module is designed in a modular structure for use as an IP block. A general working knowledge
of the IP bus signals and bus control is assumed in the writing of this document.
Figure 6-1
shows the organization of the BDLC module. The Tx/Rx shadow register function as Buffers
provide storage for data received and data to be transmitted onto the J1850 bus. The Protocol Handler is
responsible for the encoding and decoding of data bits and special message symbols during transmission
and reception. The MUX Interface provides the link between the BDLC digital section and the analog
Physical Interface. The wave shaping, driving and digitizing of data is performed by the Physical Interface.
The Physical Interface is not implemented in the BDLC module and must be provided externally.
The main functional blocks of the BDLC module are explained in greater detail in the following sections.
Use of the BDLC module in message networking fully implements the SAE Standard J1850 Class B Data
Communication Network Interface specification.
MPC5125 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor
6-1