MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 318

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

DRAM Controller
11.3.2.2
11.3.2.2.1
11-10
DRAM_COMMAND_TIME
DRAM_BANK_PRE_TIME
DRAM_REFRESH_TIME
Address: Base + 0x0004
Reset
Reset
W
W
R
R
[15:0]
Field
[7:0]
[7:0]
16
0
0
0
Timing Configuration
DDR Time Configuration Register 0 (DDR_TIME_CONFIG0)
17
0
0
1
Figure 11-4. DDR Time Configuration Register 0 (DDR_TIME_CONFIG0)
DRAM_COMMAND_TIME[7:0]
18
0
0
2
Refresh interval of the DRAM. Program in this register the number of CSB clocks between any two
refresh requests. This register should contain the maximum number of CSB clocks between two
refresh requests.
The average time in CSB clock periods between two refreshes to the DRAM is this number.
Time-out after sending a command to the DRAM in bypass mode. For command sent to the DRAM
using the DDR_COMMAND and DDR_COMPACT_COMMAND register, the normal checking of the
timing parameters is not done. Instead, any new command to the DRAM is disabled for
DRAM_COMMAND_TIME[7:0] dram clock periods. This parameter needs to be programmed for
the worst-case time-out.
Time-out. Any active bank, that has no outstanding requests, is automatically precharged by the
DRAM controller after this time-out has elapsed since the last access to the bank. This time can be
set short, which results in open banks being precharged quite fast to long, which results in open
banks left open for a long time. The value is a time count in DRAM clock periods.
Table 11-8. DDR_TIME_CONFIG0 field descriptions
19
0
0
3
MPC5125 Microcontroller Reference Manual, Rev. 2
20
4
0
0
21
0
0
5
DRAM_REFRESH_TIME[15:0]
22
0
0
6
23
0
0
7
24
Description
8
0
0
25
9
0
0
DRAM_BANK_PRE_TIME[7:0]
10
26
0
0
11
27
0
0
12
28
0
0
Freescale Semiconductor
Access: User read/write
13
29
0
0
14
30
0
0
15
31
0
0