MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 975

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale Semiconductor
Setting up the MII Mgmt for a read cycle to PHY’s MII Mgmt register (write the PHY’s address and Register address),
other information about the link is also returned (Extend Status, No pre, Remote Fault, An Ability, Link status, extend
read the MII Mgmt AN Link Partner Base Page Ability register and check bits 9 and 10 (Half and Full Duplex)
MII Mgmt AN Link Partner Base Page Ability ---> [0000_0000_0000_0000_0000_00X_1110_0000]
read the MII Mgmt AN Expansion register and check bits 13 and 14 (NP Able and Page Rx’d)
Perform an MII Mgmt read cycle of AN Link Partner Base Page Ability Register (Optional)
the PHY Status control register is at address 0x2 and lets say the PHY Address is 0x2
(Uses the PHY address (2) and Register address (2) placed in MIIMADD register),
(Uses the PHY address (2) and Register address (6) placed in MIIMADD register),
(Uses the PHY address (2) and Register address (5) placed in MIIMADD register),
MII Mgmt AN Expansion ---> [0000_0000_0000_0000_0000_0000_0000_0110]
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 14-185. RMII Mode Register Initialization Steps (continued)
(Uses the TBI address and Register address placed in MIIMADD register),
RBASE0–RBASE7[LLLL_LLLL_LLLL_LLLL_LLLL_LLLL_LLLL_L000]
TBASE0–TBASE7[LLLL_LLLL_LLLL_LLLL_LLLL_LLLL_LLLL_L000]
Initialize (Empty) Receive Descriptor ring and fill with empty buffers
Initialize (Empty) Transmit Descriptor ring and fill buffers with Data
MIIMSTAT ---> [0000_0000_0000_0000_0000_0010_0001_0000]
MIIMSTAT ---> [0000_0000_0000_0000_0000_0000_0010_0000]
MACCFG1[0000_0000_0000_0000_0000_0000_0000_0101]
DMACTRL[0000_0000_0000_0000_0000_0000_0000_0000]
MIIMADD[0000_0000_0000_0000_0000_0010_0000_0010]
MIIMADD[0000_0000_0000_0000_0000_0010_0000_0110]
MIIMADD[0000_0000_0000_0000_0000_0010_0000_0101]
GADDR n [0000_0000_0000_0000_0000_0000_0000_0000]
Perform an MII Mgmt read cycle of AN Expansion Register
IEVENT[0000_0000_0000_0000_0000_0000_0000_0000]
RCTRL[0000_0000_0000_0000_0000_0000_0000_0000]
IMASK[0000_0000_0000_0000_0000_0000_0000_0000]
read the MIIMSTAT register and check bit 10 (AN Done)
Check to see if PHY has completed Auto-Negotiation
Perform an MII Mgmt read cycle of Status Register
Perform an MII Mgmt read cycle (0ptional)
read the MIIMSTAT register and verify that
Initialize DMACTRL (Optional)
Initialize GADDR n (Optional)
Initialize RBASE0–RBASE7,
Initialize TBASE0–TBASE7,
Set MIIMCOM[Read Cycle]
Set MIIMCOM[Read Cycle]
Set MIIMCOM[Read Cycle]
Set MIIMCOM[Read Cycle]
Initialize RCTRL (Optional)
Initialize IMASK (Optional)
Enable Transmit Queues
Enable Receive Queues
Clear IEVENT register,
Enable Rx and Tx,
Initialize RQUEUE
Initialize TQUEUE
Ability)
Enhanced Three-Speed Ethernet Controllers
14-227