MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1034

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PCI Bus Interface
16-8
PCI_GNT[4:0]
PCI_IDSEL
PCI_IRDY
Signal
Table 16-2. PCI Interface Signals—Detailed Signal Descriptions (continued)
I/O
I/O Initiator ready. The initiator ready signal is both an input and output signal on this PCI controller.
O PCI bus grant. Output signals on this PCI controller when the arbiter is enabled. When the arbiter is
O As outputs for the bidirectional initiator ready, these signals operate as described below.
I Initialization device select. The initialization device select signal is an input signal on this PCI controller.
I As inputs for the bidirectional initiator ready, these signals operate as described below.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
disabled PCI_GNT0 is an input signal. Note that PCI_GNT[ n ] is a point-to-point signal. Every master
has its own bus grant signal.
Note: These signals are also used as reset configuration signals as described in
It is used as a chip select during configuration read and write transactions.
Meaning
Meaning
Meaning
Meaning
Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.2
Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.2
Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.2
Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev
State
State
State
State
“Power-On Reset Configuration."
Asserted—Indicates that this PCI controller has granted control of the PCI bus to agent n .
Negated—Indicates that this PCI controller has not granted control of the PCI bus to agent n .
Asserted—Indicates this PCI controller is being selected as a target of a configuration read
Negated—Indicates this PCI controller is not being selected as a target of configuration
Asserted—Indicates that this PCI controller, acting as a PCI master, can complete the
Negated—Indicates that the PCI target needs to wait before this PCI controller, acting as a
Asserted—Indicates another PCI master is able to complete the current data phase of a
Negated—If PCI_FRAME is asserted, indicates a wait cycle from another master. If
or write transactions.
read or write transactions.
current data phase of a PCI transaction. During a write, this PCI controller asserts
PCI_IRDY to indicate that valid data is present on the data bus. During a read, this
PCI controller asserts PCI_IRDY to indicate that it is prepared to accept data.
PCI master, can complete the current data phase. During a write, this PCI controller
negates PCI_IRDY to insert a wait cycle when it cannot provide valid data to the
target. During a read, this PCI controller negates PCI_IRDY to insert a wait cycle
when it cannot accept data from the target.
transaction.
PCI_FRAME is negated, indicates the PCI bus is idle.
Description
Freescale Semiconductor
Section 4.4.3,