MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1305

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

20.4.13 Auto CMD12 Error Status Register (AUTOC12ERR)
When IRQSTAT[AC12E] is set, the host driver checks this register to identify what kind of error Auto
CMD12 indicated. This register is valid only when IRQSTAT[AC12E] is set.
Offset: 0x03C (AUTOC12ERR)
Freescale Semiconductor
Reset
CNIBAC12E
W
AC12EBE
AC12TOE
R
AC12CE
AC12NE
AC12IE
25–26
Field
0–23
0
24
27
28
29
30
31
Reserved
Command not issued by Auto CMD12 error. This bit is set when CMD_wo_DAT is not executed due to an
Auto CMD12 error (D04–D01).
0 No error
1 Not Issued
Reserved
Auto CMD12 index error. Occurs if the command index error occurs in response to a command.
0 No error
1 Error, the CMD index in response is not CMD12
Auto CMD12 CRC error. Occurs when detecting a CRC error in the command response.
0 No CRC error
1 CRC error met in Auto CMD12 response
Auto CMD12 end bit error. Occurs when detecting that the end bit of command response is 0 when it should
be 1.
0 No error
1 End bit error generated
Auto CMD12 timeout error. Occurs if no response is returned within 64 SDHC_CLK cycles from the end bit
of the command. If this bit is set, the other error status bits (2–4) are meaningless.
0 No error
1 Time out
Auto CMD12 not executed. If a memory multiple block data transfer is not started due to command error,
this bit is not set because it is not necessary to issue Auto CMD12. Setting this bit means eSDHC cannot
issue Auto CMD12 to stop the memory multiple block data transfer due to some error. If this bit is set, the
other error status bits (1–4) are meaningless.
0 Executed
1 Not executed
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Figure 20-15. Auto CMD12 Error Status Register (AUTOC12ERR)
Table 20-20. AUTOC12ERR Field Descriptions
—
All zeros
Description
23
AC12E
CNIB
24
Enhanced Secure Digital Host Controller
25 26
—
AC12
IE
27
AC12
CE
28
AC12
EBE
29
Access: Read
AC12
TOE
30
20-31
AC12
NE
31