MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 77

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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Freescale Semiconductor
USB Mode (USBMODE) ................................................................................................... 21-29
Endpoint Setup Status (ENDPTSETUPSTAT) ................................................................... 21-30
Endpoint Initialization (ENDPTPRIME) ............................................................................ 21-31
Endpoint Flush (ENDPTFLUSH) ....................................................................................... 21-32
Endpoint Status (ENDPTSTATUS)..................................................................................... 21-32
Endpoint Complete (ENDPTCOMPLETE) ........................................................................ 21-33
Endpoint Control 0 (ENDPTCTRL0) ................................................................................. 21-34
Endpoint Control 1 to 5 (ENDPTCTRLn) .......................................................................... 21-35
Snoop 1 and Snoop 2 (SNOOPn)........................................................................................ 21-36
Age Count Threshold (AGE_CNT_THRESH)................................................................... 21-38
Priority Control (PRI_CTRL) ............................................................................................. 21-38
System Interface Control Register (SI_CTRL)................................................................... 21-39
USB General-Purpose Register (CONTROL) .................................................................... 21-39
Periodic Schedule Organization.......................................................................................... 21-42
Frame List Link Pointer Format.......................................................................................... 21-43
Asynchronous Schedule Organization ................................................................................ 21-43
Isochronous Transaction Descriptor (iTD) ......................................................................... 21-44
Split-Transaction Isochronous Transaction Descriptor (siTD) ........................................... 21-48
Queue Element Transfer Descriptor (qTD)......................................................................... 21-52
Queue Head Layout ............................................................................................................ 21-56
Frame Span Traversal Node Structure ................................................................................ 21-60
Derivation of Pointer into Frame List Array....................................................................... 21-66
General Format of Asynchronous Schedule List ................................................................ 21-67
Frame Boundary Relationship Between HS Bus and FS/LS Bus ....................................... 21-67
Relationship of Periodic Schedule Frame Boundaries to Bus Frame Boundaries .............. 21-68
Example Periodic Schedule ................................................................................................ 21-70
Example Association of iTDs to Client Request Buffer ..................................................... 21-73
Generic Queue Head Unlink Scenario ................................................................................ 21-78
Asynchronous Schedule List with Annotation to Mark Head of List................................. 21-79
Example Mapping of qTD Buffer Pointers to Buffer Pages ............................................... 21-81
Host Controller Asynchronous Schedule Split-Transaction State Machine ....................... 21-84
Split Transaction, Interrupt Scheduling Boundary Conditions ........................................... 21-87
General Structure of EHCI Periodic Schedule Utilizing Interrupt Spreading .................... 21-88
Example Host Controller Traversal of Recovery Path via FSTNs...................................... 21-90
Split Transaction State Machine for Interrupt..................................................................... 21-93
Split Transaction, Isochronous Scheduling Boundary Conditions ..................................... 21-99
siTD Scheduling Boundary Examples .............................................................................. 21-101
Split Transaction State Machine for Isochronous ............................................................. 21-104
End Point Queue Head Organization ................................................................................ 21-117
Endpoint Queue Head Layout........................................................................................... 21-118
Endpoint Transfer Descriptor (dTD)................................................................................. 21-120
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
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