MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 426

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Programmable Interrupt Controller (PIC)
9.4.3
The eight MSGRs, described in
send 32-bit messages to one or more processors. A messaging interrupt is generated by writing an MSGR
if the corresponding MER bit is set and the interrupt is not masked. Reading a MSGR or writing a 1 to the
status bit clears the interrupt.
9.4.4
There are eight shared MSIRs, described in
(MSIR0–MSIR7),” that indicate which of the interrupt sources sharing the MSI register have pending
interrupts. Up to 32 sources can share any individual MSI register. A shared message signaled interrupt is
generated by writing to Shared Message Signaled Interrupt Index Register (MSIIR) fields SRS and IBS.
This register is primarily intended to support inbound PCI Express message signaled interrupts (MSIs)
when the PCI Express controller is configured as a root complex (RC).
MSIIR[SRS] selects the associated MSIR and MSIIR[IBS] selects the interrupt flag/bit in that register that
is to be set. The corresponding interrupt needs to be unmasked for the interrupt to occur. A read to an MSIR
clears the all of its flags.
9.4.5
Whenever the PCI Express controller is in root complex mode and it receives an inbound INTx asserted
or negated message transaction, it asserts or negates an equivalent internal INTx signal to the PIC. This
INTx virtual-wire interrupt signaling mechanism replaces the PCI standard sideband interrupts (INTA,
INTB, INTC, and INTD) that historically were connected to the IRQn external interrupt inputs. The
internal INTx signals from the PCI Express controller are logically combined with the interrupt request
(IRQn) signals so that they share the same OpenPIC external interrupt controlled by the associated
EIVPRn and EIDRn registers.
Table 9-50
9-56
details the association of INTx signals to IRQn signals.
Message Interrupts
Shared Message Signaled Interrupts
PCI Express INTx/IRQ n Sharing
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
PCI Express Number
Table 9-50. PCI Express INTx/IRQ n Sharing
Section 9.3.5.1, “Message Registers
PCI Express 1
PCI Express 2
Section 9.3.6.1, “Shared Message Signaled Interrupt Registers
INTC
INTD
INTC
INTD
INTx
INTA
INTB
INTA
INTB
IRQ n
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
(MSGR0–MSGR7),” can be used to
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