MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 626

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DUART
Figure 12-6
Table 12-8
12.3.1.5
The UIIRs indicate when an interrupt is pending from the corresponding UART and what type of interrupt
is active. They also indicate if the FIFOs are enabled.
The DUART prioritizes interrupts into four levels and records these in the corresponding UIIR. The four
levels of interrupt conditions in order of priority are:
See
12-8
Bits
0–3
4
5
6
7
1. Receiver line status
2. Received data ready/character time-out
3. Transmitter holding register empty
4. Modem status
Table 12-10
Offset UART0: 0x501, UART1: 0x601
Reset
ETHREI Enable transmitter holding register empty interrupt.
ERDAI
ERLSI
Name
EMSI
W
R
—
describes the fields of UIER.
shows the bits in the UIER.
Interrupt ID Registers (UIIR n ) (ULCR[DLAB] = 0)
Reserved.
Enable modem status interrupt.
0 Mask interrupts caused by UMSR[DCTS] being set
1 Enable and assert interrupts when the clear-to-send bit in the UART modem status register (UMSR)
0 Mask interrupts when ULSR’s overrun, parity error, framing error or break interrupt bits are set
1 Enable and assert interrupts when ULSR’s overrun, parity error, framing error or break interrupt bits are
0 Mask interrupt when ULSR[THRE] is set
1 Enable and assert interrupts when ULSR[THRE] is set
0 Mask interrupt when new receive data is available or receive data time out has occurred
1 Enable and assert interrupts when a new data character is received from the external device and/or a
for more details.
Enable receiver line status interrupt.
Enable received data available interrupt.
0
changes state
set
time-out interrupt occurs in the FIFO mode
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Figure 12-6. Interrupt Enable Register (UIER)
—
Table 12-8. UIER Field Descriptions
3
All zeros
Description
EMSI
4
ERLSI
5
ETHREI
Freescale Semiconductor
Access: Read/Write
6
ERDAI
7