MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 795

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Offset eTSEC1:0x2_4110;
Reset
14.5.3.2.4
The TXIC register enables and configures the operational parameters for interrupt coalescing associated
with transmitted frames.
Table 14-19
1
Freescale Semiconductor
11–15
16–31
3–10
Bits
The term ‘system clock’ refers to CCB clock/2.
W
0
1
2
R
eTSEC3:0x2_6110
ICEN ICCS —
0
Name
ICEN
ICCS Interrupt coalescing timer clock source.
ICFT
ICTT
—
—
describes the fields of the TXIC register.
1
Transmit Interrupt Coalescing Register (TXIC)
Interrupt coalescing enable
0 Interrupt coalescing is disabled. Interrupts are raised as they are received.
1 Interrupt coalescing is enabled. If the eTSEC transmit frame interrupt is enabled (IMASK[TXFEN] is set),
0 The coalescing timer advances count every 64 eTSEC Tx interface clocks (TSEC n _GTX_CLK).
1 The coalescing timer advances count every 64 system clocks
Reserved
Interrupt coalescing frame count threshold. While interrupt coalescing is enabled (TXIC[ICEN] is set), this
value determines how many frames are transmitted before raising an interrupt. The eTSEC threshold counter
is reset to ICFT following an interrupt. The value of ICFT must be greater than zero to avoid unpredictable
behavior.
Reserved
Interrupt coalescing timer threshold. While interrupt coalescing is enabled (TXIC[ICEN] is set), this value
determines the maximum amount of time after transmitting a frame before raising an interrupt. If frames have
been transmitted but the frame count threshold has not been met, an interrupt is raised when the threshold
timer reaches zero. The threshold timer is reset to the value in this field and begins counting down upon
transmission of the first frame having its TxBD[I] bit set. The threshold value is represented in units of 64 clock
periods as specified by the timer clock source (TXIC[ICCS[). The value of ICTT must be greater than zero to
avoid unpredictable behavior.
2
an interrupt is raised when the threshold number of frames is reached (defined by TXIC[ICFT]) or when the
threshold timer expires (determined by TXIC[ICTT]).
operation.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
3
Figure 14-14
ICFT
Figure 14-14. TXIC Register Definition
Table 14-19. TXIC Field Descriptions
describes the definition for the TXIC register.
10 11
—
All zeros
Description
15 16
1
. This mode is recommended for FIFO
Enhanced Three-Speed Ethernet Controllers
ICTT
Access: Read/Write
14-47
31