MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1014

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DMA Controller
15.4.1.2.2
Extended direct single-write start mode has the same functionality as the basic direct single-write start
mode with the addition of stride capabilities. The bit settings are also the same with the exception of
MRn[XFE] being set. Striding on the source address can be accomplished by setting SATRn[SSME] and
setting the desired stride size and distance in SSRn. Striding on the destination address can be
accomplished by setting DATRn[DSME] and setting the desired stride size and distance in DSRn.
15.4.1.2.3
In extended chaining mode, the software must first build list and link descriptor segments in memory. Then
CLSDARn and ECLSDARn must be initialized to point to the first list descriptor in memory. The DMA
controller loads list descriptors and link descriptors from memory prior to a DMA transfer. The DMA
controller begins the transfer according to the link descriptor information loaded. Once the current link
descriptor is finished, the DMA controller reads the next link descriptor from memory and begins another
DMA transfer. If the current link descriptor is the last in the list, the DMA controller reads the next list
descriptor in memory. The transfer is finished if the current link descriptor is the last one in the last list in
memory or if an error condition occurs. The sequence of events to start and complete a transfer in extended
chaining mode is as follows:
15.4.1.2.4
In the extended mode, the single-write start feature allows a chain to be started by writing the current list
descriptor pointer. Setting MRn[CDSM/SWSM] causes MRn[CS] to be set automatically when
CLSDARn is written. (Note that ECLSDARn must be written first so that the full 36-bit descriptor address
is present when the chain starts.) The sequence of events to start and complete an extended chain using
single-write start mode is as follows:
15-28
1. Build link and list descriptor segments in memory.
2. Poll the channel state (see
3. Initialize CLSDARn and ECLSDARn to point to the first list descriptor in memory.
4. Clear the mode register channel transfer mode bit, MRn[CTM], to indicate chaining mode.
5. Clear, then set the mode register channel start bit, MRn[CS], to start the DMA transfer.
6. SRn[CB] is set by the DMA controller to indicate the DMA transfer is in progress.
7. SRn[CB] is automatically cleared by the DMA controller after finishing the transfer of the last
1. Set MRn[CDSM/SWSM], MRn[CTM], and MRn[XFE] to indicate extended chaining and
2. Build list and link descriptor segments in local memory.
3. Poll the channel state (see
MRn[XFE] must be set to indicate extended DMA mode. Other control parameters may also be
initialized in the mode register.
descriptor segment, or if the transfer is aborted (MRn[CA] transitions from a 0 to 1), or if an error
occurs during any of the transfers.
single-write start mode. Also other control parameters may be initialized in the mode register.
Extended Direct Single-Write Start Mode
Extended Chaining Mode
Extended Chaining Single-Write Start Mode
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table
Table
15-23), to confirm that the specific DMA channel is idle.
15-23), to confirm that the specific DMA channel is idle.
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