MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 328

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DDR Memory Controller
8.4.1.35
The memory data path read capture low register, shown in
data path during error capture.
Table 8-41
8.4.1.36
The memory data path read capture ECC register, shown in
were on the data bus when an error was detected.
Table 8-42
8.4.1.37
The memory error detect register stores the detection bits for multiple memory errors, single- and
multiple-bit ECC errors, and memory select errors. It is a read/write register. A bit can be cleared by
8-54
0–31
Bits
16–31
0–15
Bits
Offset 0xE24
Offset 0xE28
Reset
Reset
W
W
R
R
Name
ECLD Error capture low data path. Captures the low word of the data path when errors are detected.
Name
0
0
ECE
describes the CAPTURE_DATA_LO fields.
describes the CAPTURE_ECC fields.
—
Figure 8-36. Memory Data Path Read Capture Low Register (CAPTURE_DATA_LO)
Memory Data Path Read Capture Low (CAPTURE_DATA_LO)
Memory Data Path Read Capture ECC (CAPTURE_ECC)
Memory Error Detect (ERR_DETECT)
Figure 8-37. Memory Data Path Read Capture ECC Register (CAPTURE_ECC)
Reserved
Error capture ECC. Captures the ECC bits on the data path whenever errors are detected.
0:7—8-bit ECC for 1st 16 bits in 16-bit bus mode; should be ignored for 32-bit and 64-bit mode
8:15—8-bit ECC for 2nd 16 bits in 16-bit bus mode; 1st 32 bits in 32-bit bus mode; should be ignored for
16:23—8-bit ECC for 3rd 16 bits in 16-bit bus mode; should be ignored for 32-bit and 64-bit mode
24:31—8-bit ECC for 4th 16 bits in 16-bit bus mode; 2nd 32 bits in 32-bit bus mode; all 64-bits in 64-bit bus
64-bit bus mode
mode
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 8-41. CAPTURE_DATA_LO Field Descriptions
—
Table 8-42. CAPTURE_ECC Field Descriptions
15 16
All zeros
All zeros
ECLD
Description
Description
Figure
Figure
8-37, stores the ECC syndrome bits that
8-36, stores the low word of the read
ECE
Freescale Semiconductor
Access: Read/Write
Access: Read/Write
31
31