MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 517

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

be written with the bit lengths of AAD and IV, respectively. The bit length of text data should be written
to the data size register, up to a size of 2
the input FIFO and the result (text data) read from the output FIFO as available. At the end, the final MAC
tag is read from context registers 1–2.
10.7.1.12 AESU Key Registers
The format of the AESU key registers is shown in
bytes of key data, with the first 8 bytes of key data written to key 1.Any key data written to bytes beyond
the key size (as specified in the key size register) is ignored. The key data registers are cleared when the
AESU is reset or re-initialized. If these registers are modified during message processing, a context error
is generated.
The key registers may be read when changing context in decrypt mode. To resume processing, the value
read must be written back to the key registers and the “restore decrypt key” bit must be set in the mode
register. This eliminates the overhead of expanding the key prior to starting decryption when switching
context.
Freescale Semiconductor
Reset
Reset
Reset
Reset
Field
Field
Field
Field
Addr
Addr
Addr
Addr
R/W
R/W
R/W
R/W
0
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Figure 10-31. AESU Key Registers
19
bits. IV, AAD, and text data in that order should be sent through
AESU 0x3_4400
AESU 0x3_4408
AESU 0x3_4410
AESU 0x3_4418
Key 1U Register
Key 2U Register
Key 1L Register
Key 2L Register
Figure
R/W
R/W
R/W
R/W
0
0
0
0
10-31. These registers may hold 16, 24, or 32
Security Engine (SEC) 3.0
63
Key
Key
Key
Key
1U
2U
1L
2L
10-87