MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 954

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Three-Speed Ethernet Controllers
Table 14-170
14-206
Offset Bits
0–1
typedef unsigned short uint_16; /* choose 16-bit native type */
typedef unsigned int uint_32; /* choose 32-bit native type */
typedef struct rxbd_struct {
} rxbd;
0
1
2
3
4
5
6
7
uint_16 flags;
uint_16 length;
uint_32 bufptr;
describes the fields of the RxBD.
Name
RO1
W
—
M
E
F
L
I
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Empty, written by the eTSEC (when cleared) and by the user (when set).
0 The data buffer associated with this BD is filled with received data, or data reception is aborted due
1 The data buffer associated with this BD is empty, or reception is currently in progress.
Receive software ownership bit.
This field is reserved for use by software. This read/write bit is not modified by hardware, nor does its
value affect hardware.
Wrap, written by user.
0 The next buffer descriptor is found in the consecutive location.
1 The next buffer descriptor is found at the location defined in RBASE.
Interrupt, written by user.
0 No interrupt is generated after this buffer is serviced.
1 IEVENT[RXB] or IEVENT[RXF] are set after this buffer is serviced. This bit can cause an interrupt
Last in frame, written by the eTSEC.
0 The buffer is not the last in a frame.
1 The buffer is the last in a frame.
First in frame, written by the eTSEC.
0 The buffer is not the first in a frame.
1 The buffer is the first in a frame.
Reserved
Miss, written by the eTSEC. (This bit is valid only if the L-bit is set and eTSEC is in promiscuous mode.)
This bit is set by the eTSEC for frames that were accepted in promiscuous mode, but were flagged as
a “miss” by the internal address recognition; thus, while in promiscuous mode, the user can use the
M-bit to quickly determine whether the frame was destined to this station.
0 The frame was received because of an address recognition hit.
1 The frame was received because of promiscuous mode.
Table 14-170. Receive Buffer Descriptor Field Descriptions
to an error condition. The status and length fields have been updated as required.
if enabled (IMASK[RXBEN] or IMASK[RXFEN]). If the user wants to be interrupted only if RXF
occurs, then the user must disable RXB (IMASK[RXBEN] is cleared) and enable RXF
(IMASK[RXFEN] is set).
Figure 14-159. Mapping of RxBDs to a C Data Structure
Description
Freescale Semiconductor