MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 545

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.7.4.7
The DEU interrupt mask register, controls the setting of bits in the DEU interrupt status register, as
described in
then the corresponding interrupt status register bit is always zero.
Masking an error bit allows for a hardware error condition to go potentially undetected. Therefore, extreme
care should be taken when masking errors, as invalid results may be produced. It is recommended that
errors only be masked during debug operation. This register may be reset by resetting the DEU.
Freescale Semiconductor
Offset 0x3_2038
Reset
0-49
W
Bits
R
50
51
52
53
54
55
56
0
Section 10.7.4.6, “DEU Interrupt Status
DEU Interrupt Mask Register
Name
ERE
DSE
KPE
KSE
ME
—
CE
IE
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 10-52. DEU Interrupt Mask Register Field Descriptions
—
Reserved
Key Parity Error. The defined parity bits in the keys written to the key registers did not reflect
odd parity correctly. (Note that key register 2 and key register 3 are only checked for parity if the
appropriate DEU mode register bit indicates triple DES.
0 Key parity error enabled
1 Key parity error disabled
Internal Error. An internal processing error was detected while performing encryption.
0 Internal error enabled
1 Internal error disabled
Early Read Error. The DEU IV Register was read while the DEU was performing encryption.
0 Early read error enabled
1 Early read error disabled
Context Error. A DEU key register,or the key size register, the data size register, the mode
register, or IV register was modified while DEU was performing encryption.
0 Context error enabled
1 Context error disabled
Key Size Error. An inappropriate value (8 being appropriate for single DES, and 16 and 24 being
appropriate for Triple DES) was written to the DEU key size register
0 Key size error enabled
1 Key size error disabled
Data Size Error (DSE). A value that is not a multiple of 64 bits was written to the DEU data size
register if ECB, CBC, or CFB mode is selected. If OFB mode is selected, any data size value is
permitted.
0 Data size error enabled
1 Data size error disabled
Mode Error. An illegal value was detected in the mode register.
0 Mode error enabled
1 Mode error disabled
Figure 10-62. DEU Interrupt Mask Register
48
KPE IE ERE CE KSE DSE ME AE OFE IFE IFU IFO OFU OFO KPE
49
50
51
Register”. If a DEU interrupt mask register bit is set,
1000
52
Description
53
54
55
56
57
58
59
Security Engine (SEC) 3.0
60
Access: Read/Write
61
62
10-115
63