MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1414

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Universal Serial Bus Interfaces
Queue heads use the Queue Element Transfer Descriptor (qTD) structure defined in
“Queue Element Transfer Descriptor (qTD).”
One queue head is used to manage the data stream for one endpoint. The queue head structure contains
static endpoint characteristics and capabilities. It also contains a working area from where individual bus
transactions for an endpoint are executed. Each qTD represents one or more bus transactions, which is
defined in the context of the EHCI specification as a transfer.
The general processing model for the host controller's use of a queue head is simple:
If the host controller encounters errors during a transaction, the host controller will set one of the error
reporting bits in the queue head's Status field. The Status field accumulates all errors encountered during
the execution of a qTD (that is, the error bits in the queue head Status field are sticky until the transfer
(qTD) has completed). This state is always written back to the source qTD when the transfer is complete.
On transfer (for example, buffer or halt conditions) boundaries, the host controller must auto-advance
(without software intervention) to the next qTD. Additionally, the hardware must be able to halt the queue
so no additional bus transactions will occur for the endpoint and the host controller will not advance the
queue.
21.6.10.1 Buffer Pointer List Use for Data Streaming with qTDs
A qTD has an array of buffer pointers, which is used to reference the data buffer for a transfer. The EHCI
specification requires that the buffer associated with the transfer be virtually contiguous. This means that
if the buffer spans more than one physical page, it must obey the following rules:
21-80
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Read a queue head,
Execute a transaction from the overlay area,
Write back the results of the transaction to the overlay area
Move to the next queue head.
The first portion of the buffer must begin at some offset in a page and extend through the end of
the page.
The remaining buffer cannot be allocated in small chunks scattered around memory. For each 4K
chunk beyond the first page, each buffer portion matches to a full 4K page. The final portion, which
may only be large enough to occupy a portion of a page, must start at the top of the page and be
contiguous within that page.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Freescale Semiconductor
Section 21.5.5,