MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 922

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Three-Speed Ethernet Controllers
The receive timer threshold counter is reset to the value in RXIC[ICTT] and begins counting down on
receiving the frame following an interrupt.
14.6.3.11 Inter-Frame Gap Time
If a station must transmit, it waits until the LAN becomes silent for a specified period (inter-frame gap, or
IFG). The minimum inter-packet gap (IPG) time for back-to-back transmission is set by
IPGIFG[Back-to-Back Inter-Packet-Gap]. The receiver receives back-to-back frames with the minimum
interframe gap (IFG) as set in IPGIFG[Minimum IFG Enforcement]. If multiple frames are ready to
transmit, the Ethernet controller follows the minimum IPG as long as the following restrictions are met:
If the TxBD alignment restrictions are not met, the back-to-back IPG may be as many as 32 cycles due to
BD refetching. If the TxBD size restriction is not met, the back-to-back IPG may be significantly longer.
In half-duplex mode, after a station begins sending, it continually checks for collisions on the LAN. If a
collision is detected, the station forces a jam signal (all ones) on its frame and stops transmitting. Collisions
usually occur close to the beginning of a packet. The station then waits a random time period (back-off)
before attempting to send again. After the back-off completes, the station waits for silence on the LAN
(carrier sense negated) and then begins retransmission (retry) on the LAN. Retransmission begins 36 bit
times after carrier sense is negated for at least 60 bit times. If the frame is not successfully sent within a
specified number of retries, an error is indicated (collision retry limit exceeded).
If a queue is actively transmitting, and multiple BDs are ready to transmit, the ethernet controller satisfies
the minimum IPG (96 bit times) as long as the following restrictions are met by software:
If multiple BDs per frame are used, BD fetching may result in a gap between frames of up to 32 cycles if
the fetch delay causes the amount of data in the TxFIFO to fall below the transmit threshold (1 KB).
If TCP Offload is enabled (TCTRL[TUCSEN]=1 or TCTRL[IPCSEN]=1), the entire frame must be
loaded in the TxFIFO before transmission can start. For frames longer than 1200 bytes, this delay in start
of transmission can result in extra inter-packet gaps, with the delay increasing with size of frame.
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The next transmit buffer descriptor address (TBPTRn) for a ring is located at a 16-byte aligned
address when the ring starts transmitting.
All BDs for any multiple-BD frame reside in the same cache line.
TCP/UDP and IP Checksum generation are disabled in each frame's TxFCB, or in TCTRL, or
frames are limited to 1200 bytes in length.
Each TxBD[Data Length] >= 64 bytes.
The next BD is always ready when fetched by the controller.
Frames use a single BD.
TCP/UDP and IP Checksum generation are disabled in each frame's TxFCB, or in TCTRL, or
frames are limited to 1200 bytes in length.
Each TxBD[Data Length] >= 64 bytes.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Freescale Semiconductor