MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 634

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DUART
12.3.1.11
The UMSRs track the status of the modem (or external peripheral device) clear to send (CTS) signal for
the corresponding UART.
Figure 12-13
Table 12-17
12-16
Bits Name
5
6
7
Bits
0–2
4–6
3
7
OE
DR
PE
Offset UART0: 0x506, UART10: 0x606
Reset
Name
DCTS Clear to send.
CTS
W
—
—
R
Parity error.
0 This bit is cleared when ULSR is read or when a new character is loaded into the URBR.
1 Unexpected parity value encountered when receiving data. In FIFO mode, the character with the error is at the
Overrun error.
0 This bit is cleared when ULSR is read.
1 Before the URBR is read, the URBR was overwritten with a new character. The old character is loss. In FIFO
Data ready.
0 This bit is cleared when URBR is read or when all of the data in the receiver FIFO is read.
1 A character has been received in the URBR or the receiver FIFO.
describes the fields of the UMSRs.
shows the bits in the UMSRs.
top of the FIFO.
mode, the receiver FIFO is full (regardless of the receiver FIFO trigger level setting) and a new character has
been received into the internal receiver shift register. The old character was overwritten by the new character.
Data in the receiver FIFO was not overwritten.
Reserved.
Clear to send. Represents the inverted value of the CTS input pin from the external peripheral device
0 Corresponding CTS n is negated
1 Corresponding CTS n is asserted. The modem or peripheral device is ready for data transfers.
Reserved.
0 No change on the corresponding CTS n signal since the last read of UMSR[CTS]
1 The CTS n value has changed, since the last read of UMSR[CTS]. Causes an interrupt if UIER[EMSI] is set
Modem Status Registers (UMSR n )
to detect this condition
0
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 12-16. ULSR Field Descriptions (continued)
—
Figure 12-13. Modem Status Register (UMSR)
Table 12-17. UMSR Field Descriptions
2
CTS
3
Description
All zeros
Description
4
—
Freescale Semiconductor
6
Access: Read only
DCTS
7