MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 754

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Three-Speed Ethernet Controllers
14.4
This section defines the eTSEC interface signals. The buses are described using the bus convention used
in IEEE 802.3 because the PHY follows this same convention. (That is, TxD[7:0] means 0 is the lsb.) Note
that except for external physical interfaces the buses and registers follow a big-endian format, where 0
denotes the msb.
Each eTSEC network interface supports multiple options:
14-6
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The options supported are promiscuous, broadcast, exact unicast address match, exact unicast
virtual address match to support router redundancy, and multicast hash match. For detailed
descriptions refer to
eTSEC supports automatic LAN-initiated wake-up during power management through the AMD
Magic Packet™ protocol, as described in
Receive frame parsing options
Frame parsing options are to disable parsing (no TCP/IP off-load), IP header parsing, and TCP or
UDP parsing. Parsing must be enabled to make use of receive queue filing algorithms. The options
are detailed in
Receive queue selection options
Received frames are by default sent to a single buffer descriptor ring. If multiple receive queues
are enabled, a receive queue filer can be programmed with selection criteria to differentiate
received frames and file them to different buffer descriptor rings. See
Service (QoS) Provision,”
TCP/IP transmit options
Frames for transmission may be sent as-is, with IP header processing, or TCP header processing.
The transmit buffer descriptors, described in
(TxBD),”
described in
Transmit queue selection options
The options supported are single transmit queue, priority-based queue selection, and modified
weighted round-robin queueing. These options are described further in
“Transmit Control Register (TCTRL).”
RMON support
Standard Ethernet interface management information base (MIBs) can be generated through the
RMON MIB counters.
Internal loop back supported for all interfaces except when configured for half-duplex operation
Internal loop back mode is selected through the loop back bit in the MACCFG1 register. See
Section 14.7.1, “Interface Mode Configuration,”
The MII option requires 18 I/O signals (including the MDIO and MDC MII management interface)
and supports both a data and a management interface to the PHY (transceiver) device. The MII
option supports both 10- and 100-Mbps Ethernet rates.
The GMII option is a superset of the MII signals and supports a 1000-Mbps Ethernet rate.
External Signals Description
enable these options and operate with parameters prepended to frame buffers, as
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Section 14.6.4, “TCP/IP Off-Load.”
Section 14.6.4, “TCP/IP Off-Load.”
Section 14.6.3.7, “Frame Recognition.”
for detailed descriptions.
Section 14.6.3.8, “Magic Packet Mode.”
Section 14.6.8.2, “Transmit Data Buffer Descriptors
for details.
Section 14.6.5, “Quality of
Section 14.5.3.2.1,
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