MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 474

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Security Engine (SEC) 3.0
10.4.4.4
Each channel contains a fetch FIFO to store a queue of pointers to descriptors which the channel will
process. A pointer is added to the queue by writing to the FFER.
The register is shown in
In channel-driven access, the host CPU creates a descriptor in memory containing all relevant mode and
location information for the SEC, then launches the descriptor by writing its address to the fetch FIFO
enqueue register.
The fetch FIFO can hold up to 24 descriptor pointers at a time. When the current descriptor’s processing
is finished, the next fetch FIFO entry is read and the descriptor located at FETCH_ADR is launched.
10-44
Offset Channel 1: 0x3_1148, Channel 2: 0x3_1248,
Reset
W
R
28-31
28-31
32–63 CUR_DES_PTR_ADRS Current Descriptor Pointer Address. Pointer to system memory location of the
32–63
0–27
0–27
Bits
Bits
Channel 3: 0x3_1348, Channel 4: 0x3_1448
0
FETCH_ADR Fetch Address. Pointer to system memory location of the first byte of descriptor to be
Fetch FIFO Enqueue Register (FFER)
Name
EPTR
—
Name
EPTR
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
—
Table 10-17. Fetch FIFO Enqueue Register Field Descriptions
Figure
Reserved, must be cleared.
Extended Pointer: Concatenated as the top 4 bits of the FETCH_ADR when EAE is high (see
the EAE bit description in
processed.
Table 10-16. Current Descriptor Pointer Register Fields
—
15 16
Figure 10-14. Fetch FIFO Enqueue Register (FFER)
10-14, and the fields are described in
Reserved, must be cleared.
Extended Pointer: Concatenated as the top 4 bits of the CUR_DES_PTR_ADRS
when EAE is high (see the EAE bit description in
current descriptor. This field reflects the starting location in system memory of the
descriptor currently loaded into the DB. This value is updated whenever the channel
requests a fetch of a descriptor from the controller.
The value from the fetch FIFO is transferred to the current descriptor pointer
register immediately after the fetch is completed.
This address is used as the destination for writeback of the modified header dword,
if header writeback notification is enabled.
27 28
Table
EPTR
10-11).
All zeros
31 32
Description
Description
Table
CUR_DES_PTR_ADRS
Table
10-17.
10-11).
Freescale Semiconductor
Access: Write only
63