MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1227

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 18-18
transfer (SPMODEx[CPx] = 0).
Freescale Semiconductor
12–15
16–19 CS n BEF CS assertion time in bits before frame start (i.e. before clock toggles)
20–23 CS n AFT CS assertion time in bits after frame end (i.e. after clock finishes toggling)
24–28 CS n CG Clock gap
29–31
(From Master)
Bits
11
(From Slave)
CSx/SPISEL
SPI_MOSI
SPI_MISO
SPI_CLK
SPI_CLK
Name
POL n
LEN n
—
shows the eSPI transfer format in which SPI_CLK starts toggling in the middle of the
NOTE: Q = Undefined Signal.
CS n Polarity.
1 Asserted Low, Negated High
0 Asserted High, Negated Low.
Character length in bits per character. Must be between 00011 (4 bits) and 01111 (16 bits). A value
less than 4 causes erratic behavior.
Example: CS0BEF =0010 inserts 2bits time gap between CS0 assertion to clock toggle
Example: CS0AFT =0010 inserts 2bits time gap between clock stop to CS0 negation
insert gaps between transmitted frames according to this size (during this time, chip select is negated).
Chip select is negated minimum time of 1 bit time.
Example: CS0CG =00101 inserts 5+1=6 bits time gap between every two consecutive frames
Reserved, should be cleared.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
(CI = 0)
(CI = 1)
Figure 18-18. eSPI Transfer Format with SPMODEx[CPx] = 0
msb
msb
Table 18-8. SPMODE n Field Descriptions
Description
Enhanced Serial Peripheral Interface
lsb
lsb
Q
18-13