MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1354

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Universal Serial Bus Interfaces
Section 21.3.2.9, “Endpoint List Address Register (ENDPOINTLISTADDR)—Non-EHCI,”
information.
21.3.2.9
This register is not defined in the EHCI specification. In device mode, this register contains the address of
the top of the endpoint list in system memory. Bits 10–0 of this register cannot be modified by the system
software and always return zeros when read. The memory structure referenced by this physical memory
pointer is assumed to be 64-bytes. The queue head is actually a 48-byte structure, but must be aligned on
64-byte boundary. However, the ENDPOINTLISTADDR[EPBASE] has a granularity of 2 Kbytes, so in
practice the queue head should be 2-Kbyte aligned.
Note that this register is shared between the host and device mode functions. In device mode, it is the
ENDPOINTLISTADDR register; in host mode, it is the ASYNCLISTADDR register. See
Section 21.3.2.8, “Current Asynchronous List Address Register (ASYNCLISTADDR),”
information.
21-20
Offset 0x158
Reset
31–11
31–5
10–0
Offset 0x158
Reset
Bits
Bits
4–0
W
R
W
R
31
31
ASYBASE
EPBASE
Name
Name
—
—
Endpoint List Address Register (ENDPOINTLISTADDR)—Non-EHCI
Figure 21-14. Current Asynchronous List Address (ASYNCLISTADDR)
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Link pointer low (LPL). These bits correspond to memory address signals [31:5]. This field may only
reference a queue head (QH). Only used by the host controller.
Reserved, should be cleared.
Reserved, should be cleared.
Endpoint list address. Address of the top of the endpoint list.
Table 21-17. ENDPOINTLISTADDR Register Field Descriptions
Figure 21-15. Endpoint List Address (ENDPOINTLISTADDR)
Table 21-16. ASYNCLISTADDR Register Field Descriptions
EPBASE
ASYBASE
All zeros
All zeros
Description
Description
11 10
Freescale Semiconductor
Access: Read/Write
5
—
Access: Read/Write
for more
4
for more
—
0
0