MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 619

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 12
DUART
This chapter describes the dual universal asynchronous receiver/transmitters (DUART). It describes the
functional operation, the initialization sequence, and the programming details for the DUART registers
and features.
12.1
The DUART consists of two universal asynchronous receiver/transmitters (UARTs). The UARTs act
independently; all references to UART refer to one of these receiver/transmitters. Each UART is clocked
by the platform (CCB) clock. The DUART programming model is compatible with the PC16552D.
The UART interface is point to point, meaning that only two UART devices are attached to the connecting
signals. As shown in
12.1.1
The DUART includes these distinctive features:
Freescale Semiconductor
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Receive and transmit buffers
Clear to send (CTS) input port and request to send (RTS) output port for data flow control
16-bit counter for baud rate generation
Interrupt control logic
Full-duplex operation
Programming model compatible with original PC16450 UART and PC16550D (improved version
of PC16450 that also operates in FIFO mode)
PC16450 register reset values
FIFO mode for both transmitter and receiver, providing 16-byte FIFOs
Serial data encapsulation and decapsulation with standard asynchronous communication bits
(START, STOP, and parity)
Maskable transmit, receive, line status, and modem status interrupts
Software-programmable baud generators that divide the platform clock by 1 to (2
generate a 16x clock for the transmitter and receiver engines
Overview
Features
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Figure
12-1, each UART module consists of the following:
16
– 1) and
12-1