MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 415

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 9-41
9.3.7.5
The MIVPRs have the same fields and format as the GTVPRs, except they apply to messaging interrupts.
See
Table 9-42
Freescale Semiconductor
Offset MIVPR0: 0x1600; MIVPR1: 0x1620; MIVPR2: 0x1640; MIVPR3: 0x1660
Reset
3–29
Bits
Bits
30
31
0
1
2
0
1
W
R
Section 9.4.1, “Flow of Interrupt Control,”
MIVPR4: 0x1680; MIVPR5: 0x16A0; MIVPR6: 0x16C0; MIVPR7: 0x16E0
MSK
Name
1
CI0
CI1
0
EP
P1
P0
—
Name
MSK
A
describes the IIDR fields.
describes the MIVPRn fields.
A
1
0
External signal. Allows internal interrupt to be serviced externally.
0 Interrupt is not routed to IRQ_OUT.
1 Interrupt is routed to IRQ_OUT for external service.
Critical interrupt 0. See
0 Processor core 0 does not receive this interrupt.
1 Directs the internal interrupt to processor core 0 by causing the cint0 output signal from the PIC to assert.
Critical interrupt 1. See
single-processor implementations.
0 Processor core 1 does not receive this interrupt.
1 Directs the internal interrupt to processor core 1 by causing the cint1 output signal from the PIC to assert.
Reserved, should be cleared.
Processor core 1. Indicates whether processor core 1 receives the interrupt through int.
0 Processor core 1 does not receive this interrupt.
1 Directs the interrupt to processor core 1 through the assertion of int1 .
Note: Reserved in single-processor implementations.
Processor core 0. Indicates whether processor core 0 receives the interrupt.
0 Processor core 0 does not receive this interrupt.
1 Directs the interrupt to processor core 0 through the assertion of int0 .
The default destination is for processor core 0 to receive this external interrupt after the PIC is reset.
Messaging Interrupt Vector/Priority Registers (MIVPR n )
0
2
Mask. Mask interrupts from this source. MSK affects only interrupts routed to int .
0 An interrupt request is generated if the corresponding IPR bit is set.
1 Further interrupts from this source are disabled.
Activity. Indicates an interrupt has been requested or is in service. The VECTOR and PRIORITY values
should not be changed while this bit is set. Affects only interrupts routed to int .
0 No current interrupt activity associated with this source.
1 The interrupt field for this source is set in the IPR or ISR.
0
Figure 9-42. Messaging Interrupt Vector/Priority Registers (MIVPR n )
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
0
0
0
—
0
Section 9.1.2, “Interrupts to the Processor Core,”
Section 9.1.2, “Interrupts to the Processor Core,”
0
Table 9-42. MIVPR n Field Descriptions
Table 9-41. IIDR n Field Descriptions
0
0
11 12
0
0
PRIORITY
for information on IPR and ISR.
0
0
Description
15 16
0
Description
0
0
0
0
0
0
Programmable Interrupt Controller (PIC)
for more information.
for more information. Reserved in
0
VECTOR
0
0
0
0
0
Access: Mixed
0
0
0
9-45
31
0