MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 559

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.7.5.11 KEU ICV_In Register (KEUICV)
If ICV checking is required, then the value to be compared with the computed f9 MAC value must be
written to the KEU ICV_In register before data size is written. As the KEU ICV_In register is in between
IV_1 and IV_2, any descriptor operation that loads IV_2 must also load ICV_In. If CICV = 0, the ICV_In
register should be loaded with 0x0000_0000_0000_0000.
10.7.5.12 KEU IV_2 Register (FRESH) (KEUIV2)
The KEU IV_2 register, shown in
initialization phase of the 3GPP f9 algorithm. This value is ignored when the f8 algorithm is selected. The
FRESH value must be written to bits 0:31 of the KEU IV_2 register before a new message to be processed
with 3GPP f9 is started. After the initialization phase has been completed, the KEU IV_2 register is no
longer used during message processing. The KEU IV_2 register need not be written during context
switches.
10.7.5.13 KEU Context Data Registers (KEUC n )
The KEU includes six 64-bit KEU context data registers that store the running context used to process a
message. The KEU context data registers must be read when changing context and are restored to their
original values to resume processing of a partial message. For f8 and 3GPP f9 modes, all 64-bit KEU
context data registers must be read to retrieve context, and all six registers must be written back to restore
context. The context must be written prior to the key data. If the any of the KEU context data registers are
written during message processing, a context error is generated. All KEU context data registers are cleared
when a hard/soft reset or initialization is performed.
Freescale Semiconductor
Reset
Field
Addr
R/W
0
It is the responsibility of the user to ensure that fields of the KEU IV_1
register are programmed correctly in accordance with the algorithm
selected.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
FRESH
Figure 10-74. KEU IV_2 Register (FRESH)
Figure
10-74, holds the f9 value, FRESH, which is used during the
NOTE
KEU 0x3_E110
31
R/W
0
32
00000000
Security Engine (SEC) 3.0
63
10-129