MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 597

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

All I
1
11.3.1
This section describes the I
Freescale Semiconductor
0x100–
I
0x100 to 0x114.
Offset
0x00C
0x000
0x004
0x008
0x010
0x014
0x114
2
C2 has the same memory-mapped registers that are described for I
2
C registers are one byte wide. Reads and writes to these registers must be byte-wide operations.
I2CADR—I
I2CFDR—I
I2CCR—I
I2CSR—I
I2CDR—I
I2CDFSRR—I
I
2
Register Descriptions
C2 Registers
Reserved bits should always be written with the value they returned when
read. That is, the register should be programmed by reading the value,
modifying appropriate fields, and writing back the value. The return value
of the reserved fields should not be assumed, even though the reserved fields
return zero.
This note does not apply to the I
2
2
2
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
C status register
C control register
C data register
2
2
C frequency divider register
C address register
2
1
C digital filter sampling rate register
2
C registers in detail.
I
2
C Register
Table 11-3. I
Block Base Address: 0x0_3000
Block Base Address: 0x0_3000
I
I
2
2
2
C1 Registers
C2 Registers
C data register (I2CDR).
NOTE
2
C Memory Map
2
C1 from 0x000 to 0x014, except the offsets range from
Access
Mixed
Mixed
R/W
R/W
R/W
R/W
Reset
0x00
0x00
0x00
0x81
0x00
0x10
11.3.1.5/11-10
11.3.1.6/11-11
Section/Page
11.3.1.1/11-6
11.3.1.2/11-6
11.3.1.3/11-7
11.3.1.4/11-9
I
2
C Interfaces
11-5