MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1541

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

23.5.1.4
Many blocks in the MPC8536E can dynamically turn off clocks within the block when sections of the
block are idle. This feature is always enabled and occurs automatically.
23.5.1.5
As described in
shut down certain functional blocks within the MPC8536E when they are not needed in a particular
system. DEVDISR can be written by the e500 core or by an external master. Powering down a block in
this way turns off all clocks to that block.
DEVDISR was designed with the expectation that, once initialized by software, it would be modified only
by a hard system reset (HRESET). It is recommended that this register be written only during system
initialization. Blocks disabled by DEVDISR must not be re-enabled without a hard reset. (Setting
DEVDISR[TB] disables the core’s timer facilities, and setting DEVDISR[E500] places the core in the
core_stopped state in which it does not respond to interrupts.) The results of re-enabling previously
disabled blocks (by clearing the corresponding DEVDISR field) without a hard reset are undefined.
23.5.1.6
e500 software can place the device in doze, nap, or sleep power-down states by writing to HID0 in the
core. In addition, external masters can write to the memory-mapped POWMGTCSR in the MPC8536E to
cause the device to enter doze, sleep or deep sleep modes.
23.5.1.6.1
In doze mode, the e500 core suspends instruction execution, significantly reducing the power consumption
of the core. Snooping of the L1 data cache is still supported and thus the data in the data cache is kept
coherent. Interrupts directed to the core as described in are monitored by the device and cause the
MPC8536E to use the defined handshake mechanism to exit the core from doze mode to allow the core to
recognize and process the interrupt; however, unless the interrupt subroutine turns off (or masks) the
control bits that enabled doze mode (MSR[WE], and HID0[DOZE]), the device re-enters doze mode after
the interrupt has been serviced.
The e500 core’s timer facilities are still enabled during doze mode, and core time base interrupts can be
generated. All device logic external to the core remains fully operational in doze mode. Additionally,
ASLEEP and READY pins are both negated.
Freescale Semiconductor
Dynamic Power Management
Shutting Down Unused Blocks
Software-Controlled Power-Down States
Functional blocks disabled using DEVDISR cannot respond to
configuration accesses. Any access to configuration, control, and status
registers of a disabled block is a programming error.
Doze Mode
Section 23.4.1.10, “Device Disable Register (DEVDISR),”
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
NOTE
DEVDISR provides a way to
Global Utilities
23-49