MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 315

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 8-27
Freescale Semiconductor
13–15 WRLVL_DQSEN DQS/DQS delay after margining mode is programmed (t
9–11
Bits
1–4
5–7
12
0
8
WRLVL_ODTEN ODT delay after margining mode is programmed (t
WRLVL_MRD
WRLVL_EN
describes the DDR_WRLVL_CNTL fields.
Name
—
—
—
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Write Leveling Enable. This bit determines if write leveling is used. If this bit is set, then the DDR
controller performs write leveling immediately after initializing the DRAM. This bit should only be
set if DDR3 memory is used (DDR_SDRAM_CFG[SDRAM_TYPE] = 3’b111).
0 Write leveling is not used
1 Write leveling is used
Reserved, should be cleared.
First DQS pulse rising edge after margining mode is programmed (t
many cycles to wait after margining mode has been programmed before the first DQS pulse may
be issued. This field is only relevant when DDR_WRLVL_CNTL[WRLVL_EN] is set.
000
001
010
011
100
101
110
111
Reserved, should be cleared.
wait after margining mode has been programmed until ODT may be asserted.This field is only
relevant when DDR_WRLVL_CNTL[WRLVL_EN] is set.
000
001
010
011
100
101
110
111
Reserved, should be cleared.
cycles to wait after margining mode has been programmed until DQS may be actively driven. This
field is only relevant when DDR_WRLVL_CNTL[WRLVL_EN] is set.
000
001
010
011
100
101
110
111
Table 8-27. DDR_WRLVL_CNTL Field Descriptions
1 clocks
2 clocks
4 clocks
8 clocks
16 clocks
32 clocks
64 clocks
128 clocks
1 clocks
2 clocks
4 clocks
8 clocks
16 clocks
32 clocks
64 clocks
128 clocks
1 clocks
2 clocks
4 clocks
8 clocks
16 clocks
32 clocks
64 clocks
128 clocks
Description
WL_ODTEN
WL_DQSEN
). Determines how many cycles to
). Determines how many
WL_MRD
DDR Memory Controller
). Determines how
8-41