MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 351

Manufacturer Part Number

BOARD DEV SYSTEM MPC8536E

Manufacturer

Freescale Semiconductor

PowerQUICC III™r

Board, Software and Documentation

Processor Series

Data Bus Width

Maximum Clock Frequency

Operating Supply Voltage

- 0.3 V to + 1.21 V

Maximum Operating Temperature

Data Ram Size

Interface Type

Program Memory Type

DDR2, DDR3, SDRAM

Program Memory Size

Digital Ic Case Style

Supply Voltage Range

0.95V To 1.05V

Rohs Compliant

For Use With/related Products

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

code; the second corresponds to SDMODE. The Mode Register Set cycle time is set to 2 DRAM cycles.

To reduce loading, registered DIMMs latch the DDR SDRAM control signals internally before using them

to access the array. Setting DDR_SDRAM_CFG[RD_EN] compensates for this delay on the DIMMs’

control bus by delaying the data and data mask writes (on SDRAM buses) by an extra SDRAM clock

Freescale Semiconductor

DDR SDRAM Registered DIMM Mode

shows the timing of the mode-set command. The first transfer corresponds to the ESDMODE

Application system board must assert the reset signal on DDR memory

devices until software is able to program the DDR memory controller

configuration registers, and must deassert the reset signal on DDR memory

devices before DDR_SDRAM_CFG[MEM_EN] is set. This ensures that

the DDR memory devices are held in reset until a stable clock is provided

and, further, that a stable clock is provided before memory devices are

released from reset.

MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1

Figure 8-53. DDR SDRAM Mode-Set Command Timing

DDR Memory Controller