MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1108

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PCI Express Interface Controller
17.3.2.4
The PCI Express configuration retry timeout register, shown in
period during which retries of configuration transactions which resulted in a CRS response occur.
The fields of the PCI Express configuration retry timeout register are described in
17.3.2.5
The PCI Express configuration register, shown in
controller.
17-12
Offset 0x014
Reset
Offset 0x010
Reset 0
4–31
Bits
1–3
0
W
W
R
R
RD
0
0
Name
Figure 17-5. PCI Express Configuration Retry Timeout Register (PEX_CONF_RTY_TOR)
RD
TC
—
0
1
—
PCI Express Configuration Retry Timeout Register
(PEX_CONF_RTY_TOR)
PCI Express Configuration Register (PEX_CONFIG)
0
Retry disable. This bit disables the retry of a configuration transaction that receives a CRS status response
packet.
0 Enable retry of a configuration transaction in response to receiving a CRS status response until the timeout
1 Disable retry of a configuration transaction regardless of receiving a CRS status response.
Reserved
Timeout counter. This is the value that is used to load the CRS response counter.
One TC unit is 8× the PCI Express controller clock period; that is, one TC unit is 20 ns at 400 MHz and 30 ns
at 266.66 MHz.
Timeout period based on different TC settings:
0x000_0000
0x400_FFFF
0xFFF_FFFF
0
3
counter (defined by the PEX_CONF_RTY_TOR[TC] field) has expired.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
0
4
Figure 17-6. PCI Express Configuration Register (PEX_CONFIG)
1
0
Table 17-7. PEX_CONF_RTY_TOR Field Descriptions
0
Reserved
1.34 s at 400 MHz controller clock, 2.02 s at 266.66 MHz controller clock
5.37 s at 400 MHz controller clock, 8.05 s at 266.66 MHz controller clock
0
0
0
0
—
0
0
Figure
0
All zeros
0
Description
1
17-6, contains various control switches for the
1
TC
1
Figure
1
1
17-5, contains the maximum time
1
1
1
2
6
1
Table
SAC
Freescale Semiconductor
27
1
1
Access: Read/Write
28 29
Access: Read/Write
17-7.
—
1
1
SP
30
1
1
SCC
31
31
1