MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 35

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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Number
17.3.5.2.4
17.3.5.2.5
17.3.5.2.6
17.3.6
17.3.6.1
17.3.6.2
17.3.6.3
17.3.6.4
17.3.6.5
17.3.6.5.1
17.3.6.5.2
17.3.6.6
17.3.6.6.1
17.3.6.6.2
17.3.6.7
17.3.6.7.1
17.3.6.7.2
17.3.6.8
17.3.6.8.1
17.3.6.8.2
17.3.7
17.3.7.1
17.3.7.1.1
17.3.7.1.2
17.3.7.2
17.3.8
17.3.8.1
17.3.8.1.1
17.3.8.1.2
17.3.8.1.3
17.3.8.1.4
17.3.8.1.5
17.3.8.1.6
17.3.8.1.7
17.3.8.1.8
17.3.8.1.9
17.3.8.1.10
17.3.8.2
17.3.8.2.1
17.3.8.2.2
Freescale Semiconductor
PCI Express Error Management Registers .............................................................. 17-30
PCI Express Configuration Space Access ............................................................... 17-43
PCI Compatible Configuration Headers .................................................................. 17-45
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
PCI Express Error Detect Register (PEX_ERR_DR).......................................... 17-30
PCI Express Error Interrupt Enable Register (PEX_ERR_EN) .......................... 17-32
PCI Express Error Disable Register (PEX_ERR_DISR) .................................... 17-34
PCI Express Error Capture Status Register (PEX_ERR_CAP_STAT) ............... 17-36
PCI Express Error Capture Register 0 (PEX_ERR_CAP_R0)............................ 17-36
PCI Express Error Capture Register 1 (PEX_ERR_CAP_R1)............................ 17-38
PCI Express Error Capture Register 2 (PEX_ERR_CAP_R2)............................ 17-40
PCI Express Error Capture Register 3 (PEX_ERR_CAP_R3)............................ 17-42
RC Configuration Register Access...................................................................... 17-43
EP Configuration Register Access....................................................................... 17-44
Common PCI Compatible Configuration Header Registers................................ 17-45
Type 0 Configuration Header .............................................................................. 17-51
PCI Express Inbound Window Base Address Registers (PEXIWBARn) ....... 17-27
PCI Express Inbound Window Base Extended Address Registers
PCI Express Inbound Window Attributes Registers (PEXIWARn) ................ 17-28
PEX_ERR_CAP_R0—Outbound Case........................................................... 17-37
PEX_ERR_CAP_R0—Inbound Case ............................................................. 17-37
PEX_ERR_CAP_R1—Outbound Case........................................................... 17-38
PEX_ERR_CAP_R1—Inbound Case ............................................................. 17-39
PEX_ERR_CAP_R2—Outbound Case........................................................... 17-40
PEX_ERR_CAP_R2—Inbound Case ............................................................. 17-41
PEX_ERR_CAP_R3—Outbound Case........................................................... 17-42
PEX_ERR_CAP_R3—Inbound Case ............................................................. 17-42
PCI Express Configuration Access Register Mechanism................................ 17-43
Outbound ATMU Configuration Mechanism (RC-Only) ............................... 17-44
PCI Express Vendor ID Register—Offset 0x00 .............................................. 17-45
PCI Express Device ID Register—Offset 0x02............................................... 17-45
PCI Express Command Register—Offset 0x04 .............................................. 17-46
PCI Express Status Register—Offset 0x06 ..................................................... 17-47
PCI Express Revision ID Register—Offset 0x08............................................ 17-48
PCI Express Class Code Register—Offset 0x09 ............................................. 17-49
PCI Express Cache Line Size Register—Offset 0x0C .................................... 17-49
PCI Express Latency Timer Register—0x0D.................................................. 17-50
PCI Express Header Type Register—0x0E ..................................................... 17-50
PCI Express BIST Register—0x0F ................................................................. 17-51
PCI Express Base Address Registers—0x10–0x27......................................... 17-51
PCI Express Subsystem Vendor ID Register (EP-Mode Only)—0x2C .......... 17-54
(PEXIWBEARn) ......................................................................................... 17-27
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