MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1444

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Universal Serial Bus Interfaces
is met the host controller immediately executes a start-split transaction and appropriately advances the
transaction state of siTD
not met, the host controller simply follows siTD
case of a 2b boundary case, the split-transaction of siTD
controller returns to the context of siTD
C-mask bits 0 and 1 set and an S-mask with bit 0 set. This scheduling combination is not supported and
the behavior of the host controller is undefined.
21.6.12.3.7 Split Transaction for Isochronous—Processing Example
There is an important difference between how the hardware/software manages the isochronous split
transaction state machine and how it manages the asynchronous and interrupt split transaction state
machines. The asynchronous and interrupt split transaction state machines are encapsulated within a single
queue head. The progress of the data stream depends on the progress of each split transaction. In some
respects, the split-transaction state machine is sequenced using the Execute Transaction queue head
traversal state machine.
Isochronous is a pure time-oriented transaction/data stream. The interface data structures are optimized to
efficiently describe transactions that need to occur at specific times. The isochronous split-transaction state
machine must be managed across these time-oriented data structures. This means that system software
must correctly describe the scheduling of split-transactions across more than one data structure.
Then the host controller must make the appropriate state transitions at the appropriate times, in the correct
data structures.
For example,
full-speed isochronous data stream.
This example shows the first three siTDs for the transaction stream. Since this is the case-2a frame-wrap
case, S-masks of all siTDs for this endpoint have a value of 0x10 (a one bit in micro-frame 4) and C-mask
value of 0xC3 (one-bits in micro-frames 0,1, 6 and 7). Additionally, software ensures that the Back Pointer
field of each siTD references the appropriate siTD data structure (and the Back Pointer T-bits are cleared).
21-110
siTDX
X+1
X+3
X+2
X
#
Table 21-71
Table 21-71. Example Case 2a—Software Scheduling siTDs for an IN Endpoint
S-Mask
C-Mask
S-Mask
C-Mask
S-Mask
C-Mask
S-Mask
C-Mask
Masks
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
X
, then follows siTD
illustrates a few frames worth of scheduling required to schedule a case 2a
0
1
1
1
1
1
1
1
X
Repeats previous pattern
. Also, note that software should not initialize an siTD with
2
X
Micro-Frames
[Next Pointer] to the next schedule item. If the criterion is
X
3
[Next Pointer] to the next schedule item. Note that in the
4
1
1
1
X-1
will have its Active bit cleared when the host
5
6
1
1
1
7
1
1
1
Do Start Split
Do Complete Split
Do Complete Split
Do Complete Split
InitialSplitXState
Freescale Semiconductor