MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1365

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

21.3.2.17 Endpoint Initialization Register (ENDPTPRIME)—Non-EHCI
This register is not defined in the EHCI specification. This register is used to initialize endpoints. It is only
used in device mode.
Freescale Semiconductor
Offset 0x1B0
Reset
31–22
21–16 PETB Prime endpoint transmit buffer. For each endpoint a corresponding bit is used to request that a buffer prepared
15–6
31–6
Bits
Bits
5–0
5–0
W
R
31
Name
PERB Prime endpoint receive buffer. For each endpoint, a corresponding bit is used to request a buffer prepare for a
ENDPTSETUP
—
—
Name
STAT
—
Reserved, should be cleared.
for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one
to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use
this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer.
Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PETB[5] (bit 21 of the
register) corresponds to endpoint 5.
Note that these bits will be momentarily set by hardware during hardware re-priming operations when a dTD
is retired, and the dQH is updated.
Reserved, should be cleared.
receive operation in order to respond to a USB OUT transaction. Software should write a one to the
corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use
this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer.
Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB[5] corresponds
to endpoint 5.
Note that these bits will be momentarily set by hardware during hardware re-priming operations when a dTD
is retired, and the dQH is updated.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
—
Reserved, should be cleared.
Setup endpoint status. For every setup transaction that is received, a corresponding bit in this
register is set. Software must clear or acknowledge the setup transfer by writing a one to a respective
bit after it has read the setup data from queue head. The response to a setup packet as in the order
of operations and total response time is crucial to limit bus time outs while the setup lockout
mechanism is engaged.
This register is only used in device mode.
Table 21-24. ENDPTSETUPSTAT Register Field Descriptions
Table 21-25. ENDPTPRIME Register Field Descriptions
Figure 21-23. Endpoint Initialization (ENDPTPRIME)
22 21
PETB
16 15
All zeros
Description
Description
—
Universal Serial Bus Interfaces
6
5
Access: Read/Write
PERB
21-31
0