MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 428

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Programmable Interrupt Controller (PIC)
9.4.8
The PIC is reset by a device power-on reset (POR) or by software that sets GCR[RST], either of which
causes the following:
GCR[RST] is automatically cleared when the reset sequence is complete.
9.4.8.1
A software reset can be routed to either of the cores by writing to the processor core initialization register
(PIR). This causes the assertion of the corresponding core_hreset output signal from the PIC. When this
occurs, the corresponding CTPR also gets written to 0x000F to prevent delivery of any interrupts to int.
9.5
This section contains initialization and application information for the PIC.
9.5.1
The following subsections contain information about programming PIC registers.
9.5.1.1
Most PIC control and status registers are readable and return the last value written. The exceptions to this
rule are as follows:
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All pending and in-service interrupts are cleared.
All interrupt mask bits are set.
Polarity, sense, external signal, critical interrupt, and activity fields are reset to default values.
PIR, TFRR, TCR, MER, MSR, and MSGR0–MSGR7 are cleared.
MSG and timer destination fields are set.
The interprocessor dispatch registers are cleared.
All timer base count values are reset to zero with count inhibited.
CTPR[TASKP] is reset to 0x000F, disabling delivery of interrupts that target int.
The spurious interrupt vector resets to 0xFFFF.
The PMMRs are reset to 0xFFFF.
The PIC defaults to the pass-through mode (GCR[M] = 0).
All other registers remain at their pre-reset programmed values.
Interprocessor dispatch and EOI registers, which return zeros on reads.
Activity bits (A) of the vector/priority registers reflect the status of the corresponding interrupt
source.
IACK, which returns the vector of the highest priority pending interrupt or the spurious vector
(SVR[VECTOR]) if none is pending.
Reserved fields always return 0.
Initialization/Application Information
Resetting the PIC
Programming Guidelines
Processor Core Initialization
PIC Registers
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Freescale Semiconductor