MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 728

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Local Bus Controller
13.4.4.4.6
The REDO function is useful for wait-state insertion in a long UPM routine that would otherwise need too
many RAM words. Setting the REDO bits of the RAM word to a nonzero value causes the UPM to
re-execute the current RAM word up to three more times, as defined in the REDO field of the current RAM
word.
Special care must be taken in the following cases:
13.4.4.4.7
Address lines can be controlled by the user-provided pattern in the UPM. The address multiplex (AMX)
bits in the RAM word can choose between driving the transaction address (AMX = 00), driving it
according to the multiplexing specified by the MxMR[AM] field (AMX = 10), or driving the contents of
MAR (AMX = 11) on the address signals. The next address (NA) bit of the RAM word does not affect LA
signals, unless AMX = 00 and chooses the column address for NA = 1.
In all cases, LA[27:31] of the eLBC are driven by the five lsbs of the address selected by AMX, regardless
of whether the next address (NA) bit of the RAM word is used to increment the current address. The effect
of NA = 1 is visible only when AMX = 00 chooses the column address.
Table 13-42
column address multiplexing on the LAD[16:31] signals. When AMX = 10, LAD[0:15] are driven low
during an address phase.
13-86
•
•
•
•
•
When UTA and REDO are set together, TA is asserted the number of times specified by the REDO
function.
When NA and REDO are set together, the address is incremented the number of times specified by
the REDO function.
When LOOP and REDO are set together, the loop mechanism works as usual and the line is
repeated according to the REDO function.
LAST and REDO must not be set together.
REDO should not be used within the exception routine.
shows how the RAM word AMX bits and MxMR[AM] settings can be used to affect row ×
Repeat Execution of Current RAM Word (REDO)
Address Multiplexing (AMX)
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Read single-beat cycle
Read burst cycle
Write single-beat cycle
Write burst cycle
Refresh timer expired
RUN command
Request Serviced
Table 13-41. M x MR Loop Field Use
Loop Field
WLF
WLF
RLF
RLF
RLF
TLF
Freescale Semiconductor