MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1513

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

23.4.1.12 Power Management Control and Status Register (POWMGTCSR)
The power management control and status register (POWMGTCSR) is shown in
bits for placing the MPC8536E into low power states and for controlling when it wakes up. It also contains
power management status bits.
Table 23-15
Freescale Semiconductor
Offset 0x080
Reset
Reset
Bits
2–9
10
11
12
13
14
0
1
W
W
R
R
IRQ_MSK CI_MSK
16
0
IRQ_MSK
CI_MSK
DPSLP
Name
describes the bit settings of POWMGTCSR.
JOG
DOZ
SLP
—
—
Figure 23-12. Power Management Control and Status Register (POWMGTCSR)
1
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Interrupt input mask (e500)
0 Interrupts cause the device to wake up from a low-power state.
1 Interrupts are masked as a wake-up condition. The device remains in a low-power state despite the
Critical interrupt input mask (e500)
0 Critical interrupts cause the device to wake up from a low power state.
1 Critical interrupts are masked as a wake-up condition. The device remains in a low-power state
Reserved
Jog mode
0 No Jog request
1 Jog request. (The user should not issue a Jog request when in or when entering
Deep sleep mode
0 No request to remove power to the core and the L2 in low power mode.
1 Remove power to the core and the L2 in low power mode (deep sleep mode).
Doze mode
0 No request to put device in doze mode. Note that this bit is automatically cleared on MCP, UDE,
1 Device is to be placed in doze mode. Instruction fetching is halted in the e500 core. Note that this
Reserved
Sleep mode
0 No request to put device in sleep mode.
1 Device is to be placed in sleep mode. Instruction fetching is halted, snooping of L1 caches is
presence of an interrupt request.
despite the presence of a critical interrupt.
Doze/Snap/Sleep/DeepSleep)
SRESET, core_tbint (from the core) and also int and cint if not masked.
bit is logically ORed with HID0[DOZE].
disabled, and most functional blocks are shut down in both the e500 core and the system logic.
2
—
Table 23-15. POWMGTCSR Field Descriptions
—
24
DPSLPING JOGGING
25
9
All zeros
All zeros
Description
JOG
10
26
DPSLP
—
11
27
DOZING NAPPING SLPING
DOZ
12
28
Figure
—
13
29
23-12, contains
Access: Mixed
Global Utilities
SLP
14
30
23-21
—
—
15
31