MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1161

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 17-70
17.3.8.3.16 PCI Express I/O Limit Upper 16 Bits Register—0x32
Note that this device does not support inbound I/O transactions. The I/O limit upper 16 bits register is
shown in
Table 17-71
17.3.8.3.17 Capabilities Pointer Register—0x34
The capabilities pointer identifies additional functionality supported by the device.
Offset 0x34
Reset
Freescale Semiconductor
Bits
7–0
15–0
15–0
Bits
Offset 0x32
Reset
Bits
W
R
W
Capabilities Pointer The capabilities pointer provides the offset (0x44) for additional PCI-compatible registers above the
R
Figure
I/O Limit Upper 16 Bits Specifies bits 31–16 of the I/O space ending address when the address decode type field
I/O Base Upper 16 Bits Specifies bits 31–16 of the I/O space start address when the address decode type field in
15
0
7
Name
describes the I/O base upper 16 bits register fields.
describes the I/O limit upper 16 bits register fields.
Table 17-70. PCI Express I/O Base Upper 16 Bits Register Field Description
Table 17-71. PCI Express I/O Limit Upper 16 Bits Register Field Description
Name
Name
17-73.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
common 64-byte header. Refer to
Space,” for more information.
Table 17-72. Capabilities Pointer Register Field Description
Figure 17-73. PCI Express I/O Limit Upper 16 Bits Register
1
in the I/O limit register is 0x01.
the I/O base register is 0x01.
Figure 17-74. Capabilities Pointer Register
0
I/O Limit Upper 16 Bits
Capabilities Pointer
0
Section 17.3.9, “PCI Compatible Device-Specific Configuration
All zeros
Description
0
Description
Description
1
PCI Express Interface Controller
0
Access: Read only
Access: Read only
0
0
17-65
0