MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1377

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Frame list link pointers direct the host controller to the first work item in the frame’s periodic schedule for
the current micro-frame. The link pointers are aligned on DWord boundaries within the frame list.
Figure 21-35
Frame list link pointers always reference memory objects that are 32-byte aligned. The referenced object
may be an isochronous transfer descriptor for high-speed devices, a split-transaction isochronous transfer
descriptor (for full-speed isochronous endpoints), or a queue head (used to support high-, full- and
low-speed interrupt). System software should not place non-periodic schedule items into the periodic
schedule. The least-significant bits in a frame list pointer are used to key the host controller in as to the
type of object the pointer is referencing.
The least-significant bit is the T bit (bit 0). When this bit is set, the host controller never uses the value of
the frame list pointer as a physical memory pointer. The Typ field indicates the exact type of data structure
being referenced by this pointer. The value encodings for the Typ field are given in
21.5.2
The asynchronous transfer list (based at the ASYNCLISTADDR register) is where all the control and bulk
transfers are managed. Host controllers use this list only when it reaches the end of the periodic list, the
periodic list is disabled, or the periodic list is empty.
Freescale Semiconductor
31
Asynchronous List Queue Head Pointer
shows the format for the frame list link pointer.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
AsyncListAddr
Operational
Registers
Figure 21-36. Asynchronous Schedule Organization
Typ
00
01
10
11
Figure 21-35. Frame List Link Pointer Format
Frame List Link Pointer
Table 21-37. Typ Field Encodings
Isochronous transfer descriptor
Queue head
Split transaction isochronous transfer descriptor
Frame span traversal node
H
Bulk/Control Queue Heads
Description
Universal Serial Bus Interfaces
Table
5
4
00
3
21-37.
2
Typ
1
T
0
21-43