MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1110

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PCI Express Interface Controller
17-14
23–24
Bits
18
19
20
21
22
25
26
27
28
29
ENL23 Entered L2/L3 ready state. This bit indicates that the PCI Express controller has entered L2/L3 state. This is
EXL23 Exit L2/L3 ready state. This bit indicates that the PCI Express controller has exited the L2/L3 state. This is
Name
AION
PION
AIOF
HRD
LDD
AIB
PIB
—
—
only valid in RC mode.
1 L2/L3 ready state has been entered
0 L2/L3 ready state has not been entered
only valid in RC mode.
1 Exit L2/L3 state has been detected
0 Exit L2/L3 state not detected
Reserved. Note that during normal operation, this bit may be set (falsely). The bit may be ignored and
cleared (w1c) without consequence.
Hot reset detected. This bit indicates that the PCI Express controller has detected a hot reset condition on
the link. The controller is reset and cleans up all outstanding transactions. Link retraining takes place once
hot reset state is exited. This is valid only in EP mode.
1 Hot reset request has been detected
0 Hot reset request not detected
Link down detected. This bit indicates that a link down condition has been detected. The controller is reset
and then cleans up all outstanding transactions. Link retraining takes place once the controller has cleaned
itself up. Note that for EP, this bit and HRD are typically set when a hot reset event is detected.
1 Link down has been detected
0 Link down not detected
Reserved
Attention indicator on. This bit indicates the detection of an Attention_Indicator_On message. This bit is only
valid in EP mode.
1 Attention indicator on message is detected
0 No attention indicator on message detected
Attention indicator blink. This bit indicates the detection of an Attention_Indicator_Blink message. This bit is
only valid in EP mode.
1 Attention indicator blink message is detected
0 No attention indicator blink message detected
Attention indicator off. This bit indicates the detection of an Attention_Indicator_Off message. This bit is only
valid in EP mode.
1 Attention indicator off message is detected
0 No attention indicator off message detected
Power indicator on. This bit indicates the detection of a Power_Indicator_On message. This bit is only valid
in EP mode.
1 Power indicator on message is detected
0 No power indicator on message detected
Power indicator blink. This bit indicates the detection of an Power_Indicator_Blink message. This bit is only
valid in EP mode.
1 Power indicator blink message is detected
0 No power indicator blink message detected
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 17-9. PEX_PME_MES_DR Field Descriptions (continued)
Description
Freescale Semiconductor