MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 9

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Paragraph
Number
7.2.1.9
7.3
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.4
8.1
8.2
8.2.1
8.3
8.3.1
8.3.2
8.3.2.1
8.3.2.2
8.3.2.3
8.4
8.4.1
8.4.1.1
8.4.1.2
8.4.1.3
8.4.1.4
8.4.1.5
8.4.1.6
8.4.1.7
8.4.1.8
8.4.1.9
8.4.1.10
8.4.1.11
8.4.1.12
8.4.1.13
8.4.1.14
8.4.1.15
8.4.1.16
8.4.1.17
8.4.1.18
Freescale Semiconductor
Functional Description..................................................................................................... 7-9
Initialization/Application Information ........................................................................... 7-10
Introduction...................................................................................................................... 8-1
Features ............................................................................................................................ 8-2
External Signal Descriptions ........................................................................................... 8-3
Memory Map/Register Definition ................................................................................. 8-10
I/O Arbiter.................................................................................................................... 7-9
CCB Arbiter................................................................................................................. 7-9
Transaction Queue ..................................................................................................... 7-10
Global Data Multiplexor............................................................................................ 7-10
CCB Interface ............................................................................................................ 7-10
Modes of Operation ..................................................................................................... 8-3
Signals Overview......................................................................................................... 8-3
Detailed Signal Descriptions ....................................................................................... 8-6
Register Descriptions................................................................................................. 8-12
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
ECM Error High Address Capture Register (EEHADR) ........................................ 7-9
Memory Interface Signals........................................................................................ 8-6
Clock Interface Signals.......................................................................................... 8-10
Debug Signals........................................................................................................ 8-10
Chip Select Memory Bounds (CSn_BNDS).......................................................... 8-12
Chip Select Configuration (CSn_CONFIG).......................................................... 8-13
Chip Select Configuration 2 (CSn_CONFIG_2) ................................................... 8-15
DDR SDRAM Timing Configuration 3 (TIMING_CFG_3)................................. 8-16
DDR SDRAM Timing Configuration 0 (TIMING_CFG_0)................................. 8-17
DDR SDRAM Timing Configuration 1 (TIMING_CFG_1)................................. 8-19
DDR SDRAM Timing Configuration 2 (TIMING_CFG_2)................................. 8-21
DDR SDRAM Control Configuration (DDR_SDRAM_CFG)............................. 8-23
DDR SDRAM Control Configuration 2 (DDR_SDRAM_CFG_2)...................... 8-26
DDR SDRAM Mode Configuration (DDR_SDRAM_MODE)............................ 8-29
DDR SDRAM Mode 2 Configuration (DDR_SDRAM_MODE_2)..................... 8-29
DDR SDRAM Mode Control Register (DDR_SDRAM_MD_CNTL)................. 8-30
DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) ................. 8-33
DDR SDRAM Data Initialization (DDR_DATA_INIT) ....................................... 8-33
DDR SDRAM Clock Control (DDR_SDRAM_CLK_CNTL) ............................. 8-34
DDR Initialization Address (DDR_INIT_ADDR)................................................ 8-34
DDR Initialization Enable Extended Address (DDR_INIT_EXT_ADDR) .......... 8-35
DDR SDRAM Timing Configuration 4 (TIMING_CFG_4)................................. 8-36
DDR Memory Controller
Contents
Chapter 8
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