MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1091

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16.4.2.13 PCI Error Functions
PCI provides for parity and other system errors to be detected and reported. The PCI command register
provides for selective enabling of specific PCI error detection. The PCI bus status register provides PCI
error reporting. This section describes generation and detection of parity and error reporting for the PCI
bus.
16.4.2.13.1 PCI Parity
Generating parity is not optional; it must be performed by all PCI-compatible devices. All PCI
transactions, regardless of type, calculate even parity; that is, the number of ones on the PCI_AD[31:0],
PCI_C/BE[3:0], and PCI_PAR signals all sum to an even number.
Parity provides a way to determine, on each transaction, if the initiator successfully addressed the target
and transferred valid data. The PCI_C/BE[3:0] signals are included in the parity calculation to ensure that
the correct bus command is performed (during the address phase) and correct data is transferred (during
the data phase). The agent responsible for driving the bus must also drive even parity on the PAR and
PCI_PAR64 signal one clock cycle after a valid address phase or valid data transfer, as shown in
Figure
During the address and data phases, parity covers all 32 address/data signals and 4 command/byte enable
signals, regardless of whether all lines carry meaningful information. Byte lanes not actually transferring
data must contain stable (albeit meaningless) data and are included in parity calculation. During
configuration, special-cycle, or interrupt-acknowledge commands; some address lines are not defined, but
are driven to stable values and are included in parity calculation.
Freescale Semiconductor
PCI_PAR, PCI_PAR64
16-60.
PCI_C/BE[7:0]
PCI_DEVSEL
PCI_AD[63:0]
PCI_FRAME
PCI_PERR
PCI_SERR
PCI_TRDY
PCI_IRDY
SYSCLK
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
ADDR
CMD
Figure 16-60. PCI Parity Operation
Byte Enables
DATA
ADDR
CMD
Byte Enables
DATA
PCI Bus Interface
16-65